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| author | Craig Topper <craig.topper@intel.com> | 2017-10-15 16:57:33 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-10-15 16:57:33 +0000 |
| commit | 27381173268b6d5d226ddd3429f57f10b20c58c0 (patch) | |
| tree | 4e8eb5f4bc79fec5a10298a30ec5f0d0f73061fd /llvm/lib/Target/X86/X86Subtarget.h | |
| parent | c2e2e0a678e41ce4670f8248b9faefe1cdf54b07 (diff) | |
| download | bcm5719-llvm-27381173268b6d5d226ddd3429f57f10b20c58c0.tar.gz bcm5719-llvm-27381173268b6d5d226ddd3429f57f10b20c58c0.zip | |
[X86] Remove the SlowBTMem feature flag entirely
Turns out we have no patterns on the instructions that were using this feature flag for other reasons. These instructions are slow on all modern CPUs so it seems unlikely that we will spend any effort supporting these instructions going forward. So we might as well just kill of the feature flag and just fix up the comments.
llvm-svn: 315862
Diffstat (limited to 'llvm/lib/Target/X86/X86Subtarget.h')
| -rw-r--r-- | llvm/lib/Target/X86/X86Subtarget.h | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86Subtarget.h b/llvm/lib/Target/X86/X86Subtarget.h index 5816e860e01..d866ecc2ef9 100644 --- a/llvm/lib/Target/X86/X86Subtarget.h +++ b/llvm/lib/Target/X86/X86Subtarget.h @@ -193,9 +193,6 @@ protected: /// Processor has Prefetch with intent to Write instruction bool HasPFPREFETCHWT1; - /// True if BT (bit test) of memory instructions are slow. - bool IsBTMemSlow; - /// True if SHLD instructions are slow. bool IsSHLDSlow; @@ -489,7 +486,6 @@ public: bool hasLAHFSAHF() const { return HasLAHFSAHF; } bool hasMWAITX() const { return HasMWAITX; } bool hasCLZERO() const { return HasCLZERO; } - bool isBTMemSlow() const { return IsBTMemSlow; } bool isSHLDSlow() const { return IsSHLDSlow; } bool isPMULLDSlow() const { return IsPMULLDSlow; } bool isUnalignedMem16Slow() const { return IsUAMem16Slow; } |
