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author | Eric Christopher <echristo@gmail.com> | 2015-10-08 20:10:06 +0000 |
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committer | Eric Christopher <echristo@gmail.com> | 2015-10-08 20:10:06 +0000 |
commit | 11e5983658ce90495804e7016bc95a3913c22d22 (patch) | |
tree | 9159ad85351f02019e19dbd77120a82bcd944bc1 /llvm/lib/Target/X86/X86Subtarget.h | |
parent | 437615639fef5b72164606ff59fc3d6991a50bae (diff) | |
download | bcm5719-llvm-11e5983658ce90495804e7016bc95a3913c22d22.tar.gz bcm5719-llvm-11e5983658ce90495804e7016bc95a3913c22d22.zip |
Move the MMX subtarget feature out of the SSE set of features and into
its own variable.
This is needed so that we can explicitly turn off MMX without turning
off SSE and also so that we can diagnose feature set incompatibilities
that involve MMX without SSE.
Rationale:
// sse3
__m128d test_mm_addsub_pd(__m128d A, __m128d B) {
return _mm_addsub_pd(A, B);
}
// mmx
void shift(__m64 a, __m64 b, int c) {
_mm_slli_pi16(a, c);
_mm_slli_pi32(a, c);
_mm_slli_si64(a, c);
_mm_srli_pi16(a, c);
_mm_srli_pi32(a, c);
_mm_srli_si64(a, c);
_mm_srai_pi16(a, c);
_mm_srai_pi32(a, c);
}
clang -msse3 -mno-mmx file.c -c
For this code we should be able to explicitly turn off MMX
without affecting the compilation of the SSE3 function and then
diagnose and error on compiling the MMX function.
This matches the existing gcc behavior and follows the spirit of
the SSE/MMX separation in llvm where we can (and do) turn off
MMX code generation except in the presence of intrinsics.
Updated a couple of tests, but primarily tested with a couple of tests
for turning on only mmx and only sse.
This is paired with a patch to clang to take advantage of this behavior.
llvm-svn: 249731
Diffstat (limited to 'llvm/lib/Target/X86/X86Subtarget.h')
-rw-r--r-- | llvm/lib/Target/X86/X86Subtarget.h | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86Subtarget.h b/llvm/lib/Target/X86/X86Subtarget.h index 52e68c08180..198e7fbf135 100644 --- a/llvm/lib/Target/X86/X86Subtarget.h +++ b/llvm/lib/Target/X86/X86Subtarget.h @@ -47,7 +47,7 @@ class X86Subtarget final : public X86GenSubtargetInfo { protected: enum X86SSEEnum { - NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F + NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F }; enum X863DNowEnum { @@ -64,7 +64,7 @@ protected: /// Which PIC style to use PICStyles::Style PICStyle; - /// MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported. + /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported. X86SSEEnum X86SSELevel; /// 3DNow, 3DNow Athlon, or none supported. @@ -74,6 +74,9 @@ protected: /// (generally pentium pro+). bool HasCMov; + /// True if this processor supports MMX instructions. + bool HasMMX; + /// True if the processor supports X86-64 instructions. bool HasX86_64; @@ -319,7 +322,7 @@ public: void setPICStyle(PICStyles::Style Style) { PICStyle = Style; } bool hasCMov() const { return HasCMov; } - bool hasMMX() const { return X86SSELevel >= MMX; } + bool hasMMX() const { return HasMMX; } bool hasSSE1() const { return X86SSELevel >= SSE1; } bool hasSSE2() const { return X86SSELevel >= SSE2; } bool hasSSE3() const { return X86SSELevel >= SSE3; } |