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| author | Chandler Carruth <chandlerc@gmail.com> | 2018-07-14 00:52:09 +0000 |
|---|---|---|
| committer | Chandler Carruth <chandlerc@gmail.com> | 2018-07-14 00:52:09 +0000 |
| commit | a24fe067c0ae7664a662117f0fe3e4cdad0e7e43 (patch) | |
| tree | 655887c674ea1307b4ca09e4eeb0129557c6bf6d /llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp | |
| parent | f6bcbf3d88c5af10cc40c7cd031cc53a3b1cad36 (diff) | |
| download | bcm5719-llvm-a24fe067c0ae7664a662117f0fe3e4cdad0e7e43.tar.gz bcm5719-llvm-a24fe067c0ae7664a662117f0fe3e4cdad0e7e43.zip | |
[x86/SLH] Add an assert to catch if we ever end up trying to harden
post-load a register that isn't valid for use with OR or SHRX.
llvm-svn: 337078
Diffstat (limited to 'llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp index e5325cc542a..2bbb187b293 100644 --- a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp +++ b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp @@ -1533,6 +1533,14 @@ void X86SpeculativeLoadHardeningPass::hardenPostLoad( unsigned OrOpCodes[] = {X86::OR8rr, X86::OR16rr, X86::OR32rr, X86::OR64rr}; unsigned OrOpCode = OrOpCodes[Log2_32(DefRegBytes)]; +#ifndef NDEBUG + const TargetRegisterClass *OrRegClasses[] = { + &X86::GR8RegClass, &X86::GR16RegClass, &X86::GR32RegClass, + &X86::GR64RegClass}; + assert(DefRC->hasSuperClassEq(OrRegClasses[Log2_32(DefRegBytes)]) && + "Cannot define this register with OR instruction!"); +#endif + unsigned SubRegImms[] = {X86::sub_8bit, X86::sub_16bit, X86::sub_32bit}; auto GetStateRegInRC = [&](const TargetRegisterClass &RC) { |
