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| author | Andrew V. Tischenko <andrew.v.tischenko@gmail.com> | 2018-08-09 09:23:26 +0000 |
|---|---|---|
| committer | Andrew V. Tischenko <andrew.v.tischenko@gmail.com> | 2018-08-09 09:23:26 +0000 |
| commit | 24f63bcb34b56d65e622066de7d80378600acd68 (patch) | |
| tree | 0d99baccd30af129e3e09d09800eec327d87038f /llvm/lib/Target/X86/X86Schedule.td | |
| parent | f40819ea2d4c6ee471846126e9aa60477c5bcf6d (diff) | |
| download | bcm5719-llvm-24f63bcb34b56d65e622066de7d80378600acd68.tar.gz bcm5719-llvm-24f63bcb34b56d65e622066de7d80378600acd68.zip | |
[X86] Improved sched models for X86 XCHG*rr and XADD*rr instructions.
Differential Revision: https://reviews.llvm.org/D49861
llvm-svn: 339321
Diffstat (limited to 'llvm/lib/Target/X86/X86Schedule.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86Schedule.td | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86Schedule.td b/llvm/lib/Target/X86/X86Schedule.td index ef9ce94706d..4f123a96416 100644 --- a/llvm/lib/Target/X86/X86Schedule.td +++ b/llvm/lib/Target/X86/X86Schedule.td @@ -120,6 +120,7 @@ def WriteLEA : SchedWrite; // LEA instructions can't fold loads. def WriteBSWAP32 : SchedWrite; // Byte Order (Endianness) 32-bit Swap. def WriteBSWAP64 : SchedWrite; // Byte Order (Endianness) 64-bit Swap. +def WriteXCHG : SchedWrite; // Compare+Exchange - TODO RMW support. // Integer division. defm WriteDiv8 : X86SchedWritePair; |
