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| author | Craig Topper <craig.topper@intel.com> | 2018-04-17 19:35:19 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-04-17 19:35:19 +0000 |
| commit | e56a2fc5e7ee74320eb0d218b0ba5c703696a80b (patch) | |
| tree | fd103d96ae20baa5447871460882dbf789f55494 /llvm/lib/Target/X86/X86SchedHaswell.td | |
| parent | 655e1db72239483f0ec49cc01ed9baf07374dd71 (diff) | |
| download | bcm5719-llvm-e56a2fc5e7ee74320eb0d218b0ba5c703696a80b.tar.gz bcm5719-llvm-e56a2fc5e7ee74320eb0d218b0ba5c703696a80b.zip | |
[X86] Add separate scheduling class for PSADBW instruction.
llvm-svn: 330204
Diffstat (limited to 'llvm/lib/Target/X86/X86SchedHaswell.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedHaswell.td | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td index 045aa654a86..20c4f811e38 100644 --- a/llvm/lib/Target/X86/X86SchedHaswell.td +++ b/llvm/lib/Target/X86/X86SchedHaswell.td @@ -185,6 +185,7 @@ defm : HWWriteResPair<WriteVarShuffle256, [HWPort5], 3>; defm : HWWriteResPair<WriteVarBlend, [HWPort5], 2, [2]>; defm : HWWriteResPair<WriteVarVecShift, [HWPort0, HWPort5], 2, [2, 1]>; defm : HWWriteResPair<WriteMPSAD, [HWPort0, HWPort5], 6, [1, 2]>; +defm : HWWriteResPair<WritePSADBW, [HWPort0], 5>; // String instructions. @@ -2257,7 +2258,6 @@ def: InstRW<[HWWriteResGroup89], (instregex "MMX_PMADDUBSWrr", "MMX_PMULHWirr", "MMX_PMULLWirr", "MMX_PMULUDQirr", - "MMX_PSADBWirr", "MUL_FPrST0", "MUL_FST0r", "MUL_FrST0", @@ -2271,7 +2271,6 @@ def: InstRW<[HWWriteResGroup89], (instregex "MMX_PMADDUBSWrr", "(V?)PMULHW(Y?)rr", "(V?)PMULLW(Y?)rr", "(V?)PMULUDQ(Y?)rr", - "(V?)PSADBW(Y?)rr", "(V?)RCPPSr", "(V?)RCPSSr", "(V?)RSQRTPSr", |
