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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-09-23 16:53:02 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-09-23 16:53:02 +0000 |
| commit | 22d31c5e0fcb14a8343c2bc61602fb46c3dab84f (patch) | |
| tree | ac3c281f78ff98023ebaaea582fb7f4b3e0e2f22 /llvm/lib/Target/X86/X86SchedHaswell.td | |
| parent | 0805a4fa9c93a874dffc8d4be3d57ea3d59a5354 (diff) | |
| download | bcm5719-llvm-22d31c5e0fcb14a8343c2bc61602fb46c3dab84f.tar.gz bcm5719-llvm-22d31c5e0fcb14a8343c2bc61602fb46c3dab84f.zip | |
[X86] Remove unnecessary WriteRotate overrides. NFCI.
llvm-svn: 342841
Diffstat (limited to 'llvm/lib/Target/X86/X86SchedHaswell.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedHaswell.td | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td index dfd918558ad..6313360c815 100644 --- a/llvm/lib/Target/X86/X86SchedHaswell.td +++ b/llvm/lib/Target/X86/X86SchedHaswell.td @@ -134,7 +134,7 @@ def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer shifts and rotates. defm : HWWriteResPair<WriteShift, [HWPort06], 1>; -defm : HWWriteResPair<WriteRotate, [HWPort06], 1>; +defm : HWWriteResPair<WriteRotate, [HWPort06], 2, [2], 2>; // SHLD/SHRD. defm : X86WriteRes<WriteSHDrri, [HWPort1], 3, [1], 1>; @@ -1101,14 +1101,6 @@ def HWWriteResGroup28 : SchedWriteRes<[HWPort01]> { } def: InstRW<[HWWriteResGroup28], (instrs FDECSTP)>; -def HWWriteResGroup29 : SchedWriteRes<[HWPort06]> { - let Latency = 2; - let NumMicroOps = 2; - let ResourceCycles = [2]; -} -def: InstRW<[HWWriteResGroup29], (instregex "ROL(8|16|32|64)r(1|i)", - "ROR(8|16|32|64)r(1|i)")>; - def HWWriteResGroup30 : SchedWriteRes<[HWPort0156]> { let Latency = 2; let NumMicroOps = 2; |
