[X86] Fix scheduler models to support ADD32ri in addition to ADD32ri8. Similar for all sizes of AND/OR/XOR/SUB/ADC/SBB/CMP.

llvm-svn: 320291

1 files changed, 16 insertions, 16 deletions

diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td
index b1221fc1498..5665470fd8d 100644
--- a/llvm/lib/Target/X86/X86SchedHaswell.td
+++ b/llvm/lib/Target/X86/X86SchedHaswell.td
@@ -1463,12 +1463,12 @@ def HWWriteResGroup10 : SchedWriteRes<[HWPort0156]> {
   let NumMicroOps = 1;
   let ResourceCycles = [1];
 }
-def: InstRW<[HWWriteResGroup10], (instregex "ADD(16|32|64)ri8")>;
+def: InstRW<[HWWriteResGroup10], (instregex "ADD(16|32|64)ri")>;
 def: InstRW<[HWWriteResGroup10], (instregex "ADD(16|32|64)rr(_REV)?")>;
 def: InstRW<[HWWriteResGroup10], (instregex "ADD8i8")>;
 def: InstRW<[HWWriteResGroup10], (instregex "ADD8ri")>;
 def: InstRW<[HWWriteResGroup10], (instregex "ADD8rr(_REV)?")>;
-def: InstRW<[HWWriteResGroup10], (instregex "AND(16|32|64)ri8")>;
+def: InstRW<[HWWriteResGroup10], (instregex "AND(16|32|64)ri")>;
 def: InstRW<[HWWriteResGroup10], (instregex "AND(16|32|64)rr(_REV)?")>;
 def: InstRW<[HWWriteResGroup10], (instregex "AND8i8")>;
 def: InstRW<[HWWriteResGroup10], (instregex "AND8ri")>;
@@ -1476,7 +1476,7 @@ def: InstRW<[HWWriteResGroup10], (instregex "AND8rr(_REV)?")>;
 def: InstRW<[HWWriteResGroup10], (instregex "CBW")>;
 def: InstRW<[HWWriteResGroup10], (instregex "CLC")>;
 def: InstRW<[HWWriteResGroup10], (instregex "CMC")>;
-def: InstRW<[HWWriteResGroup10], (instregex "CMP(16|32|64)ri8")>;
+def: InstRW<[HWWriteResGroup10], (instregex "CMP(16|32|64)ri")>;
 def: InstRW<[HWWriteResGroup10], (instregex "CMP(16|32|64)rr(_REV)?")>;
 def: InstRW<[HWWriteResGroup10], (instregex "CMP8i8")>;
 def: InstRW<[HWWriteResGroup10], (instregex "CMP8ri")>;
@@ -1500,7 +1500,7 @@ def: InstRW<[HWWriteResGroup10], (instregex "NEG8r")>;
 def: InstRW<[HWWriteResGroup10], (instregex "NOOP")>;
 def: InstRW<[HWWriteResGroup10], (instregex "NOT(16|32|64)r")>;
 def: InstRW<[HWWriteResGroup10], (instregex "NOT8r")>;
-def: InstRW<[HWWriteResGroup10], (instregex "OR(16|32|64)ri8")>;
+def: InstRW<[HWWriteResGroup10], (instregex "OR(16|32|64)ri")>;
 def: InstRW<[HWWriteResGroup10], (instregex "OR(16|32|64)rr(_REV)?")>;
 def: InstRW<[HWWriteResGroup10], (instregex "OR8i8")>;
 def: InstRW<[HWWriteResGroup10], (instregex "OR8ri")>;
@@ -1512,7 +1512,7 @@ def: InstRW<[HWWriteResGroup10], (instregex "SLDT64m")>;
 def: InstRW<[HWWriteResGroup10], (instregex "SMSW16m")>;
 def: InstRW<[HWWriteResGroup10], (instregex "STC")>;
 def: InstRW<[HWWriteResGroup10], (instregex "STRm")>;
-def: InstRW<[HWWriteResGroup10], (instregex "SUB(16|32|64)ri8")>;
+def: InstRW<[HWWriteResGroup10], (instregex "SUB(16|32|64)ri")>;
 def: InstRW<[HWWriteResGroup10], (instregex "SUB(16|32|64)rr(_REV)?")>;
 def: InstRW<[HWWriteResGroup10], (instregex "SUB8i8")>;
 def: InstRW<[HWWriteResGroup10], (instregex "SUB8ri")>;
@@ -1523,7 +1523,7 @@ def: InstRW<[HWWriteResGroup10], (instregex "TEST8i8")>;
 def: InstRW<[HWWriteResGroup10], (instregex "TEST8ri")>;
 def: InstRW<[HWWriteResGroup10], (instregex "TEST8rr")>;
 def: InstRW<[HWWriteResGroup10], (instregex "XCHG(16|32|64)rr")>;
-def: InstRW<[HWWriteResGroup10], (instregex "XOR(16|32|64)ri8")>;
+def: InstRW<[HWWriteResGroup10], (instregex "XOR(16|32|64)ri")>;
 def: InstRW<[HWWriteResGroup10], (instregex "XOR(16|32|64)rr")>;
 def: InstRW<[HWWriteResGroup10], (instregex "XOR8i8")>;
 def: InstRW<[HWWriteResGroup10], (instregex "XOR8ri")>;
@@ -2077,7 +2077,7 @@ def: InstRW<[HWWriteResGroup18], (instregex "ADD(16|32|64)rm")>;
 def: InstRW<[HWWriteResGroup18], (instregex "ADD8rm")>;
 def: InstRW<[HWWriteResGroup18], (instregex "AND(16|32|64)rm")>;
 def: InstRW<[HWWriteResGroup18], (instregex "AND8rm")>;
-def: InstRW<[HWWriteResGroup18], (instregex "CMP(16|32|64)mi8")>;
+def: InstRW<[HWWriteResGroup18], (instregex "CMP(16|32|64)mi")>;
 def: InstRW<[HWWriteResGroup18], (instregex "CMP(16|32|64)mr")>;
 def: InstRW<[HWWriteResGroup18], (instregex "CMP(16|32|64)rm")>;
 def: InstRW<[HWWriteResGroup18], (instregex "CMP8mi")>;
@@ -2198,11 +2198,11 @@ def HWWriteResGroup26 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
   let NumMicroOps = 4;
   let ResourceCycles = [1,1,1,1];
 }
-def: InstRW<[HWWriteResGroup26], (instregex "ADD(16|32|64)mi8")>;
+def: InstRW<[HWWriteResGroup26], (instregex "ADD(16|32|64)mi")>;
 def: InstRW<[HWWriteResGroup26], (instregex "ADD(16|32|64)mr")>;
 def: InstRW<[HWWriteResGroup26], (instregex "ADD8mi")>;
 def: InstRW<[HWWriteResGroup26], (instregex "ADD8mr")>;
-def: InstRW<[HWWriteResGroup26], (instregex "AND(16|32|64)mi8")>;
+def: InstRW<[HWWriteResGroup26], (instregex "AND(16|32|64)mi")>;
 def: InstRW<[HWWriteResGroup26], (instregex "AND(16|32|64)mr")>;
 def: InstRW<[HWWriteResGroup26], (instregex "AND8mi")>;
 def: InstRW<[HWWriteResGroup26], (instregex "AND8mr")>;
@@ -2214,17 +2214,17 @@ def: InstRW<[HWWriteResGroup26], (instregex "NEG(16|32|64)m")>;
 def: InstRW<[HWWriteResGroup26], (instregex "NEG8m")>;
 def: InstRW<[HWWriteResGroup26], (instregex "NOT(16|32|64)m")>;
 def: InstRW<[HWWriteResGroup26], (instregex "NOT8m")>;
-def: InstRW<[HWWriteResGroup26], (instregex "OR(16|32|64)mi8")>;
+def: InstRW<[HWWriteResGroup26], (instregex "OR(16|32|64)mi")>;
 def: InstRW<[HWWriteResGroup26], (instregex "OR(16|32|64)mr")>;
 def: InstRW<[HWWriteResGroup26], (instregex "OR8mi")>;
 def: InstRW<[HWWriteResGroup26], (instregex "OR8mr")>;
 def: InstRW<[HWWriteResGroup26], (instregex "POP(16|32|64)rmm")>;
 def: InstRW<[HWWriteResGroup26], (instregex "PUSH(16|32|64)rmm")>;
-def: InstRW<[HWWriteResGroup26], (instregex "SUB(16|32|64)mi8")>;
+def: InstRW<[HWWriteResGroup26], (instregex "SUB(16|32|64)mi")>;
 def: InstRW<[HWWriteResGroup26], (instregex "SUB(16|32|64)mr")>;
 def: InstRW<[HWWriteResGroup26], (instregex "SUB8mi")>;
 def: InstRW<[HWWriteResGroup26], (instregex "SUB8mr")>;
-def: InstRW<[HWWriteResGroup26], (instregex "XOR(16|32|64)mi8")>;
+def: InstRW<[HWWriteResGroup26], (instregex "XOR(16|32|64)mi")>;
 def: InstRW<[HWWriteResGroup26], (instregex "XOR(16|32|64)mr")>;
 def: InstRW<[HWWriteResGroup26], (instregex "XOR8mi")>;
 def: InstRW<[HWWriteResGroup26], (instregex "XOR8mr")>;
@@ -2355,7 +2355,7 @@ def HWWriteResGroup35 : SchedWriteRes<[HWPort06,HWPort0156]> {
   let NumMicroOps = 2;
   let ResourceCycles = [1,1];
 }
-def: InstRW<[HWWriteResGroup35], (instregex "ADC(16|32|64)ri8")>;
+def: InstRW<[HWWriteResGroup35], (instregex "ADC(16|32|64)ri")>;
 def: InstRW<[HWWriteResGroup35], (instregex "ADC(16|32|64)rr(_REV)?")>;
 def: InstRW<[HWWriteResGroup35], (instregex "ADC8i8")>;
 def: InstRW<[HWWriteResGroup35], (instregex "ADC8ri")>;
@@ -2376,7 +2376,7 @@ def: InstRW<[HWWriteResGroup35], (instregex "CMOVP(16|32|64)rr")>;
 def: InstRW<[HWWriteResGroup35], (instregex "CMOVS(16|32|64)rr")>;
 def: InstRW<[HWWriteResGroup35], (instregex "CWD")>;
 def: InstRW<[HWWriteResGroup35], (instregex "JRCXZ")>;
-def: InstRW<[HWWriteResGroup35], (instregex "SBB(16|32|64)ri8")>;
+def: InstRW<[HWWriteResGroup35], (instregex "SBB(16|32|64)ri")>;
 def: InstRW<[HWWriteResGroup35], (instregex "SBB(16|32|64)rr(_REV)?")>;
 def: InstRW<[HWWriteResGroup35], (instregex "SBB8i8")>;
 def: InstRW<[HWWriteResGroup35], (instregex "SBB8ri")>;
@@ -3033,7 +3033,7 @@ def HWWriteResGroup68 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
   let NumMicroOps = 6;
   let ResourceCycles = [1,1,1,3];
 }
-def: InstRW<[HWWriteResGroup68], (instregex "ADC(16|32|64)mi8")>;
+def: InstRW<[HWWriteResGroup68], (instregex "ADC(16|32|64)mi")>;
 def: InstRW<[HWWriteResGroup68], (instregex "ADC8mi")>;
 def: InstRW<[HWWriteResGroup68], (instregex "ADD8mi")>;
 def: InstRW<[HWWriteResGroup68], (instregex "AND8mi")>;
@@ -3056,7 +3056,7 @@ def: InstRW<[HWWriteResGroup69], (instregex "ROL(16|32|64)mCL")>;
 def: InstRW<[HWWriteResGroup69], (instregex "ROL8mCL")>;
 def: InstRW<[HWWriteResGroup69], (instregex "SAR(16|32|64)mCL")>;
 def: InstRW<[HWWriteResGroup69], (instregex "SAR8mCL")>;
-def: InstRW<[HWWriteResGroup69], (instregex "SBB(16|32|64)mi8")>;
+def: InstRW<[HWWriteResGroup69], (instregex "SBB(16|32|64)mi")>;
 def: InstRW<[HWWriteResGroup69], (instregex "SBB(16|32|64)mr")>;
 def: InstRW<[HWWriteResGroup69], (instregex "SBB8mi")>;
 def: InstRW<[HWWriteResGroup69], (instregex "SBB8mr")>;