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authorQuentin Colombet <qcolombet@apple.com>2016-05-06 21:10:53 +0000
committerQuentin Colombet <qcolombet@apple.com>2016-05-06 21:10:53 +0000
commit2728074e3c104408e140962f1aecccd10cb18c19 (patch)
treecf9ce0b5e4e1788d08438756de0f036a5464d0cb /llvm/lib/Target/X86/X86RegisterInfo.cpp
parent377fc2aa3d477122e6fa943bd0a93c9f5b26e321 (diff)
downloadbcm5719-llvm-2728074e3c104408e140962f1aecccd10cb18c19.tar.gz
bcm5719-llvm-2728074e3c104408e140962f1aecccd10cb18c19.zip
[X86] Add a new LOW32_ADDR_ACCESS_RBP register class.
ABIs like NaCl uses 32-bit addresses but have 64-bit frame. The new register class reflects those constraints when choosing a register class for a address access. llvm-svn: 268796
Diffstat (limited to 'llvm/lib/Target/X86/X86RegisterInfo.cpp')
-rw-r--r--llvm/lib/Target/X86/X86RegisterInfo.cpp10
1 files changed, 9 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp
index e32a5fdcdba..cb4170cc623 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.cpp
+++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp
@@ -166,7 +166,15 @@ X86RegisterInfo::getPointerRegClass(const MachineFunction &MF,
// we can still use 64-bit register as long as we know the high bits
// are zeros.
// Reflect that in the returned register class.
- return Is64Bit ? &X86::LOW32_ADDR_ACCESSRegClass : &X86::GR32RegClass;
+ if (Is64Bit) {
+ // When the target also allows 64-bit frame pointer and we do have a
+ // frame, this is fine to use it for the address accesses as well.
+ const X86FrameLowering *TFI = getFrameLowering(MF);
+ return TFI->hasFP(MF) && TFI->Uses64BitFramePtr
+ ? &X86::LOW32_ADDR_ACCESS_RBPRegClass
+ : &X86::LOW32_ADDR_ACCESSRegClass;
+ }
+ return &X86::GR32RegClass;
case 1: // Normal GPRs except the stack pointer (for encoding reasons).
if (Subtarget.isTarget64BitLP64())
return &X86::GR64_NOSPRegClass;
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