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| author | Craig Topper <craig.topper@intel.com> | 2019-04-15 21:06:32 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-04-15 21:06:32 +0000 |
| commit | 0495f29e42c7423f54a9e2c3a3bf3561a70990d8 (patch) | |
| tree | 54693a436ed5fdca5ce5823c48e9a0a7ef21c969 /llvm/lib/Target/X86/X86RegisterInfo.cpp | |
| parent | 77439bb1280bfbbf51098492598261d5f5d87df8 (diff) | |
| download | bcm5719-llvm-0495f29e42c7423f54a9e2c3a3bf3561a70990d8.tar.gz bcm5719-llvm-0495f29e42c7423f54a9e2c3a3bf3561a70990d8.zip | |
[X86] Limit the 'x' inline assembly constraint to zmm0-15 when used for a 512 type.
The 'v' constraint is used to select zmm0-31. This makes 512 bit consistent with 128/256-bit.a
llvm-svn: 358450
Diffstat (limited to 'llvm/lib/Target/X86/X86RegisterInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86RegisterInfo.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp index 9f5f22b5610..7dec87cdcb0 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.cpp +++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp @@ -163,6 +163,7 @@ X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC, case X86::RFP32RegClassID: case X86::RFP64RegClassID: case X86::RFP80RegClassID: + case X86::VR512_0_15RegClassID: case X86::VR512RegClassID: // Don't return a super-class that would shrink the spill size. // That can happen with the vector and float classes. |
