summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/X86/X86RegisterBankInfo.h
diff options
context:
space:
mode:
authorIgor Breger <igor.breger@intel.com>2017-03-28 09:35:06 +0000
committerIgor Breger <igor.breger@intel.com>2017-03-28 09:35:06 +0000
commitf580fce2c34461433e404b5dacad87a483d1164e (patch)
tree5c533c1f5f9e146363ca5289e657ce8be4ae3cb9 /llvm/lib/Target/X86/X86RegisterBankInfo.h
parent923e574bff006ea6a6888e1900ecc4d4a2a4ef41 (diff)
downloadbcm5719-llvm-f580fce2c34461433e404b5dacad87a483d1164e.tar.gz
bcm5719-llvm-f580fce2c34461433e404b5dacad87a483d1164e.zip
[GlobalISel][X86] support G_FRAME_INDEX instruction selection.
Summary: G_LOAD/G_STORE, add alternative RegisterBank mapping. For G_LOAD, Fast and Greedy mode choose the same RegisterBank mapping (GprRegBank ) for the G_GLOAD + G_FADD , can't get rid of cross register bank copy GprRegBank->VecRegBank. Reviewers: zvi, rovka, qcolombet, ab Reviewed By: zvi Subscribers: llvm-commits, dberris, kristof.beyls, eladcohen, guyblank Differential Revision: https://reviews.llvm.org/D30979 llvm-svn: 298907
Diffstat (limited to 'llvm/lib/Target/X86/X86RegisterBankInfo.h')
-rw-r--r--llvm/lib/Target/X86/X86RegisterBankInfo.h20
1 files changed, 20 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86RegisterBankInfo.h b/llvm/lib/Target/X86/X86RegisterBankInfo.h
index 5fcce87a71e..aaa83920b6b 100644
--- a/llvm/lib/Target/X86/X86RegisterBankInfo.h
+++ b/llvm/lib/Target/X86/X86RegisterBankInfo.h
@@ -49,12 +49,32 @@ private:
static InstructionMapping getSameOperandsMapping(const MachineInstr &MI,
bool isFP);
+ /// Track the bank of each instruction operand(register)
+ /// \return An instruction PartialMappingIdxs.
+ static void
+ getInstrPartialMappingIdxs(const MachineInstr &MI,
+ const MachineRegisterInfo &MRI, const bool isFP,
+ SmallVectorImpl<PartialMappingIdx> &OpRegBankIdx);
+
+ /// Construct the instruction ValueMapping from PartialMappingIdxs
+ /// \return true if mapping succeeded.
+ static bool
+ getInstrValueMapping(const MachineInstr &MI,
+ const SmallVectorImpl<PartialMappingIdx> &OpRegBankIdx,
+ SmallVectorImpl<const ValueMapping *> &OpdsMapping);
+
public:
X86RegisterBankInfo(const TargetRegisterInfo &TRI);
const RegisterBank &
getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
+ InstructionMappings
+ getInstrAlternativeMappings(const MachineInstr &MI) const override;
+
+ /// See RegisterBankInfo::applyMapping.
+ void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
+
InstructionMapping getInstrMapping(const MachineInstr &MI) const override;
};
OpenPOWER on IntegriCloud