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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-05-07 10:50:11 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-05-07 10:50:11 +0000 |
| commit | 3c975a0ab54fdd420d3f1c84e1c41bc35738cb53 (patch) | |
| tree | 9ea16169cd9e9ced8c557920d5b03b35156aa375 /llvm/lib/Target/X86/X86RegisterBankInfo.cpp | |
| parent | d6d3808fa4324585e6949db6e4e8cd0b323c4406 (diff) | |
| download | bcm5719-llvm-3c975a0ab54fdd420d3f1c84e1c41bc35738cb53.tar.gz bcm5719-llvm-3c975a0ab54fdd420d3f1c84e1c41bc35738cb53.zip | |
[X86] Reduce scope of variables where possible. NFCI.
Fixes cppcheck warnings.
llvm-svn: 360131
Diffstat (limited to 'llvm/lib/Target/X86/X86RegisterBankInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86RegisterBankInfo.cpp | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86RegisterBankInfo.cpp b/llvm/lib/Target/X86/X86RegisterBankInfo.cpp index 3ea4c59aa49..78fede3dcde 100644 --- a/llvm/lib/Target/X86/X86RegisterBankInfo.cpp +++ b/llvm/lib/Target/X86/X86RegisterBankInfo.cpp @@ -159,7 +159,7 @@ const RegisterBankInfo::InstructionMapping & X86RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { const MachineFunction &MF = *MI.getParent()->getParent(); const MachineRegisterInfo &MRI = MF.getRegInfo(); - auto Opc = MI.getOpcode(); + unsigned Opc = MI.getOpcode(); // Try the default logic for non-generic instructions that are either copies // or already have some operands assigned to banks. @@ -182,9 +182,6 @@ X86RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { case TargetOpcode::G_SHL: case TargetOpcode::G_LSHR: case TargetOpcode::G_ASHR: { - const MachineFunction &MF = *MI.getParent()->getParent(); - const MachineRegisterInfo &MRI = MF.getRegInfo(); - unsigned NumOperands = MI.getNumOperands(); LLT Ty = MRI.getType(MI.getOperand(0).getReg()); |
