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| author | Craig Topper <craig.topper@intel.com> | 2017-09-25 21:14:55 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-09-25 21:14:55 +0000 |
| commit | d830f276c1d877322d3bcd8c7e9e12596fcf1b5a (patch) | |
| tree | 7a9ff88886345b2c383916aef8881521079e4aa7 /llvm/lib/Target/X86/X86MCInstLower.cpp | |
| parent | 8cf757cedaacc1a327917b8ba2465091c0d3d36b (diff) | |
| download | bcm5719-llvm-d830f276c1d877322d3bcd8c7e9e12596fcf1b5a.tar.gz bcm5719-llvm-d830f276c1d877322d3bcd8c7e9e12596fcf1b5a.zip | |
[X86] Make all the NOREX CodeGenOnly instructions into postRA pseudos like the NOREX version of TEST.
llvm-svn: 314151
Diffstat (limited to 'llvm/lib/Target/X86/X86MCInstLower.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86MCInstLower.cpp | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp index 36d81128acf..7a770d6cbc5 100644 --- a/llvm/lib/Target/X86/X86MCInstLower.cpp +++ b/llvm/lib/Target/X86/X86MCInstLower.cpp @@ -604,9 +604,7 @@ ReSimplify: // Note, we are currently not handling the following instructions: // MOV64ao8, MOV64o8a // XCHG16ar, XCHG32ar, XCHG64ar - case X86::MOV8mr_NOREX: case X86::MOV8mr: - case X86::MOV8rm_NOREX: case X86::MOV8rm: case X86::MOV16mr: case X86::MOV16rm: @@ -615,9 +613,7 @@ ReSimplify: unsigned NewOpc; switch (OutMI.getOpcode()) { default: llvm_unreachable("Invalid opcode"); - case X86::MOV8mr_NOREX: case X86::MOV8mr: NewOpc = X86::MOV8o32a; break; - case X86::MOV8rm_NOREX: case X86::MOV8rm: NewOpc = X86::MOV8ao32; break; case X86::MOV16mr: NewOpc = X86::MOV16o32a; break; case X86::MOV16rm: NewOpc = X86::MOV16ao32; break; |
