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authorSimon Pilgrim <llvm-dev@redking.me.uk>2016-07-13 15:45:36 +0000
committerSimon Pilgrim <llvm-dev@redking.me.uk>2016-07-13 15:45:36 +0000
commita99368fa3540a82fd6aaf125a63a8b5c3b0674aa (patch)
tree6f04e5442a1fa6184b66a45c42e53311e084b28b /llvm/lib/Target/X86/X86MCInstLower.cpp
parent2404b1719241456b7c4a3f8c5f9ece18eebcfa48 (diff)
downloadbcm5719-llvm-a99368fa3540a82fd6aaf125a63a8b5c3b0674aa.tar.gz
bcm5719-llvm-a99368fa3540a82fd6aaf125a63a8b5c3b0674aa.zip
[X86][AVX512] Add support for VPERMILPD/VPERMILPS variable shuffle mask comments
llvm-svn: 275272
Diffstat (limited to 'llvm/lib/Target/X86/X86MCInstLower.cpp')
-rw-r--r--llvm/lib/Target/X86/X86MCInstLower.cpp35
1 files changed, 26 insertions, 9 deletions
diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp
index 00a7c2540c4..217a37d6d10 100644
--- a/llvm/lib/Target/X86/X86MCInstLower.cpp
+++ b/llvm/lib/Target/X86/X86MCInstLower.cpp
@@ -1370,10 +1370,12 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
}
break;
}
- case X86::VPERMILPSrm:
+
case X86::VPERMILPDrm:
- case X86::VPERMILPSYrm:
- case X86::VPERMILPDYrm: {
+ case X86::VPERMILPDYrm:
+ case X86::VPERMILPDZ128rm:
+ case X86::VPERMILPDZ256rm:
+ case X86::VPERMILPDZrm: {
if (!OutStreamer->isVerboseAsm())
break;
assert(MI->getNumOperands() > 5 &&
@@ -1382,16 +1384,31 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
const MachineOperand &SrcOp = MI->getOperand(1);
const MachineOperand &MaskOp = MI->getOperand(5);
- unsigned ElSize;
- switch (MI->getOpcode()) {
- default: llvm_unreachable("Invalid opcode");
- case X86::VPERMILPSrm: case X86::VPERMILPSYrm: ElSize = 32; break;
- case X86::VPERMILPDrm: case X86::VPERMILPDYrm: ElSize = 64; break;
+ if (auto *C = getConstantFromPool(*MI, MaskOp)) {
+ SmallVector<int, 8> Mask;
+ DecodeVPERMILPMask(C, 64, Mask);
+ if (!Mask.empty())
+ OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, SrcOp, Mask));
}
+ break;
+ }
+
+ case X86::VPERMILPSrm:
+ case X86::VPERMILPSYrm:
+ case X86::VPERMILPSZ128rm:
+ case X86::VPERMILPSZ256rm:
+ case X86::VPERMILPSZrm: {
+ if (!OutStreamer->isVerboseAsm())
+ break;
+ assert(MI->getNumOperands() > 5 &&
+ "We should always have at least 5 operands!");
+ const MachineOperand &DstOp = MI->getOperand(0);
+ const MachineOperand &SrcOp = MI->getOperand(1);
+ const MachineOperand &MaskOp = MI->getOperand(5);
if (auto *C = getConstantFromPool(*MI, MaskOp)) {
SmallVector<int, 16> Mask;
- DecodeVPERMILPMask(C, ElSize, Mask);
+ DecodeVPERMILPMask(C, 32, Mask);
if (!Mask.empty())
OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, SrcOp, Mask));
}
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