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authorBenjamin Kramer <benny.kra@googlemail.com>2017-09-26 10:25:27 +0000
committerBenjamin Kramer <benny.kra@googlemail.com>2017-09-26 10:25:27 +0000
commit4b2113a3034842b6035cf9c184c5602b5535b7dc (patch)
tree7adb901ebe602ade201084c7a14324f4d36f5e56 /llvm/lib/Target/X86/X86MCInstLower.cpp
parent4a5a6337f7b79c8800dc0f5d7119f17b07e527ae (diff)
downloadbcm5719-llvm-4b2113a3034842b6035cf9c184c5602b5535b7dc.tar.gz
bcm5719-llvm-4b2113a3034842b6035cf9c184c5602b5535b7dc.zip
Revert "[X86] Make all the NOREX CodeGenOnly instructions into postRA pseudos like the NOREX version of TEST."
Makes llc crash. This reverts commit r314151. llvm-svn: 314199
Diffstat (limited to 'llvm/lib/Target/X86/X86MCInstLower.cpp')
-rw-r--r--llvm/lib/Target/X86/X86MCInstLower.cpp4
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp
index 7a770d6cbc5..36d81128acf 100644
--- a/llvm/lib/Target/X86/X86MCInstLower.cpp
+++ b/llvm/lib/Target/X86/X86MCInstLower.cpp
@@ -604,7 +604,9 @@ ReSimplify:
// Note, we are currently not handling the following instructions:
// MOV64ao8, MOV64o8a
// XCHG16ar, XCHG32ar, XCHG64ar
+ case X86::MOV8mr_NOREX:
case X86::MOV8mr:
+ case X86::MOV8rm_NOREX:
case X86::MOV8rm:
case X86::MOV16mr:
case X86::MOV16rm:
@@ -613,7 +615,9 @@ ReSimplify:
unsigned NewOpc;
switch (OutMI.getOpcode()) {
default: llvm_unreachable("Invalid opcode");
+ case X86::MOV8mr_NOREX:
case X86::MOV8mr: NewOpc = X86::MOV8o32a; break;
+ case X86::MOV8rm_NOREX:
case X86::MOV8rm: NewOpc = X86::MOV8ao32; break;
case X86::MOV16mr: NewOpc = X86::MOV16o32a; break;
case X86::MOV16rm: NewOpc = X86::MOV16ao32; break;
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