Change LEA to have 5 operands for its memory operand, just

like all other instructions, even though a segment is not
allowed.  This resolves a bunch of gross hacks in the 
encoder and makes LEA more consistent with the rest of the
instruction set.

No functionality change.

llvm-svn: 107934

1 files changed, 1 insertions, 9 deletions

diff --git a/llvm/lib/Target/X86/X86MCCodeEmitter.cpp b/llvm/lib/Target/X86/X86MCCodeEmitter.cpp
index 94333aea6ac..813b8814f23 100644
--- a/llvm/lib/Target/X86/X86MCCodeEmitter.cpp
+++ b/llvm/lib/Target/X86/X86MCCodeEmitter.cpp
@@ -655,10 +655,7 @@ void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
   default: assert(0 && "Invalid segment!");
   case 0:
     // No segment override, check for explicit one on memory operand.
-    if (MemOperand != -1 &&   // If the instruction has a memory operand.
-        // FIXME: This is disgusting.
-        MI.getOpcode() != X86::LEA64r && MI.getOpcode() != X86::LEA64_32r &&
-        MI.getOpcode() != X86::LEA16r && MI.getOpcode() != X86::LEA32r) {
+    if (MemOperand != -1) {   // If the instruction has a memory operand.
       switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) {
       default: assert(0 && "Unknown segment register!");
       case 0: break;
@@ -839,11 +836,6 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
       ++FirstMemOp;  // Skip the register source (which is encoded in VEX_VVVV).
     }
 
-    // FIXME: Maybe lea should have its own form?  This is a horrible hack.
-    if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
-        Opcode == X86::LEA16r || Opcode == X86::LEA32r)
-      --AddrOperands; // No segment register
-
     EmitByte(BaseOpcode, CurByte, OS);
     
     EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),