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| author | Igor Breger <igor.breger@intel.com> | 2017-06-28 11:39:04 +0000 |
|---|---|---|
| committer | Igor Breger <igor.breger@intel.com> | 2017-06-28 11:39:04 +0000 |
| commit | d5b59cf91466c1718fa329dd6d893aafc57c9771 (patch) | |
| tree | 8f987cd17bc73a0953e2284cd5a1e90109e229e5 /llvm/lib/Target/X86/X86LegalizerInfo.cpp | |
| parent | f66840020cf5eb3ae8cefc2c8ecb0f4b7bc3ad72 (diff) | |
| download | bcm5719-llvm-d5b59cf91466c1718fa329dd6d893aafc57c9771.tar.gz bcm5719-llvm-d5b59cf91466c1718fa329dd6d893aafc57c9771.zip | |
[GlobalISel][X86] Support bitwise operations : G_AND, G_OR, G_XOR
Summary: Support G_AND, G_OR, G_XOR for i8/i16/i32/i64. Selection done via TableGen'erated code.
Reviewers: zvi, guyblank, aymanmus, m_zuckerman
Reviewed By: aymanmus
Subscribers: rovka, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D34605
llvm-svn: 306533
Diffstat (limited to 'llvm/lib/Target/X86/X86LegalizerInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86LegalizerInfo.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86LegalizerInfo.cpp b/llvm/lib/Target/X86/X86LegalizerInfo.cpp index 53215296ce6..a5fa3340c3f 100644 --- a/llvm/lib/Target/X86/X86LegalizerInfo.cpp +++ b/llvm/lib/Target/X86/X86LegalizerInfo.cpp @@ -56,7 +56,7 @@ void X86LegalizerInfo::setLegalizerInfo32bit() { const LLT s32 = LLT::scalar(32); const LLT s64 = LLT::scalar(64); - for (unsigned BinOp : {G_ADD, G_SUB, G_MUL}) + for (unsigned BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR}) for (auto Ty : {s8, s16, s32}) setAction({BinOp, Ty}, Legal); @@ -117,7 +117,7 @@ void X86LegalizerInfo::setLegalizerInfo64bit() { const LLT s32 = LLT::scalar(32); const LLT s64 = LLT::scalar(64); - for (unsigned BinOp : {G_ADD, G_SUB, G_MUL}) + for (unsigned BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR}) for (auto Ty : {s8, s16, s32, s64}) setAction({BinOp, Ty}, Legal); |
