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| author | Alexander Ivchenko <alexander.ivchenko@intel.com> | 2018-10-08 13:40:34 +0000 |
|---|---|---|
| committer | Alexander Ivchenko <alexander.ivchenko@intel.com> | 2018-10-08 13:40:34 +0000 |
| commit | 1aedf203dd17e58be86c61a6fd674b3f8d41b296 (patch) | |
| tree | 1fd75b4157f4cd464903be027f8607e597b85148 /llvm/lib/Target/X86/X86LegalizerInfo.cpp | |
| parent | 60badd75845f5ebfa68d488e1d0535b26e06749c (diff) | |
| download | bcm5719-llvm-1aedf203dd17e58be86c61a6fd674b3f8d41b296.tar.gz bcm5719-llvm-1aedf203dd17e58be86c61a6fd674b3f8d41b296.zip | |
[GlobalIsel][X86] Support G_UDIV/G_UREM/G_SREM
Support G_UDIV/G_UREM/G_SREM. The instruction selection
code is taken from FastISel with only minor tweaks to adapt
for GlobalISel.
Differential Revision: https://reviews.llvm.org/D49781
llvm-svn: 343966
Diffstat (limited to 'llvm/lib/Target/X86/X86LegalizerInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86LegalizerInfo.cpp | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86LegalizerInfo.cpp b/llvm/lib/Target/X86/X86LegalizerInfo.cpp index 4e64e8ea980..4f59e0f79a7 100644 --- a/llvm/lib/Target/X86/X86LegalizerInfo.cpp +++ b/llvm/lib/Target/X86/X86LegalizerInfo.cpp @@ -133,7 +133,8 @@ void X86LegalizerInfo::setLegalizerInfo32bit() { getActionDefinitionsBuilder(G_INTTOPTR).legalFor({{p0, s32}}); // Shifts and SDIV - getActionDefinitionsBuilder({G_SHL, G_LSHR, G_ASHR, G_SDIV}) + getActionDefinitionsBuilder( + {G_SHL, G_LSHR, G_ASHR, G_SDIV, G_SREM, G_UDIV, G_UREM}) .legalFor({s8, s16, s32}) .clampScalar(0, s8, s32); } @@ -236,9 +237,10 @@ void X86LegalizerInfo::setLegalizerInfo64bit() { .widenScalarToNextPow2(1); // Shifts and SDIV - getActionDefinitionsBuilder({G_SHL, G_LSHR, G_ASHR, G_SDIV}) - .legalFor({s8, s16, s32, s64}) - .clampScalar(0, s8, s64); + getActionDefinitionsBuilder( + {G_SHL, G_LSHR, G_ASHR, G_SDIV, G_SREM, G_UDIV, G_UREM}) + .legalFor({s8, s16, s32, s64}) + .clampScalar(0, s8, s64); // Merge/Unmerge setAction({G_MERGE_VALUES, s128}, Legal); |
