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| author | Pengfei Wang <pengfei.wang@intel.com> | 2019-05-29 02:20:37 +0000 |
|---|---|---|
| committer | Pengfei Wang <pengfei.wang@intel.com> | 2019-05-29 02:20:37 +0000 |
| commit | 818c652643411667c054fd9a929c4c07941832b5 (patch) | |
| tree | ce5e8771bc44fe8cf6723d2283cac86bc9e292d0 /llvm/lib/Target/X86/X86InstructionSelector.cpp | |
| parent | 719322411ce62662bcd3bdc5ee9deb6c2c84ffb7 (diff) | |
| download | bcm5719-llvm-818c652643411667c054fd9a929c4c07941832b5.tar.gz bcm5719-llvm-818c652643411667c054fd9a929c4c07941832b5.zip | |
[X86] Use 'llvm_unreachable' instead of nullptr in unreachable code to
avoid static check fail
RegClassOrBank is an object of RegClassOrRegBank, which is defined as
using llvm::RegClassOrRegBank = typedef PointerUnion<const
TargetRegisterClass *, const RegisterBank *>
so control flow can not get here. Use ""llvm_unreachable" here to avoid
"null pointer" confusion.
Patch by Shengchen Kan (skan)
Differential Revision: https://reviews.llvm.org/D62006
Signed-off-by: pengfei <pengfei.wang@intel.com>
llvm-svn: 361912
Diffstat (limited to 'llvm/lib/Target/X86/X86InstructionSelector.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstructionSelector.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86InstructionSelector.cpp b/llvm/lib/Target/X86/X86InstructionSelector.cpp index 61de562f8a5..e52ee03f34a 100644 --- a/llvm/lib/Target/X86/X86InstructionSelector.cpp +++ b/llvm/lib/Target/X86/X86InstructionSelector.cpp @@ -1610,8 +1610,8 @@ bool X86InstructionSelector::selectDivRem(MachineInstr &I, assert(RegTy == MRI.getType(Op1Reg) && RegTy == MRI.getType(Op2Reg) && "Arguments and return value types must match"); - const RegisterBank *RegRB = RBI.getRegBank(DstReg, MRI, TRI); - if (!RegRB || RegRB->getID() != X86::GPRRegBankID) + const RegisterBank &RegRB = *RBI.getRegBank(DstReg, MRI, TRI); + if (RegRB.getID() != X86::GPRRegBankID) return false; const static unsigned NumTypes = 4; // i8, i16, i32, i64 @@ -1709,7 +1709,7 @@ bool X86InstructionSelector::selectDivRem(MachineInstr &I, const DivRemEntry &TypeEntry = *OpEntryIt; const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex]; - const TargetRegisterClass *RegRC = getRegClass(RegTy, *RegRB); + const TargetRegisterClass *RegRC = getRegClass(RegTy, RegRB); if (!RBI.constrainGenericRegister(Op1Reg, *RegRC, MRI) || !RBI.constrainGenericRegister(Op2Reg, *RegRC, MRI) || !RBI.constrainGenericRegister(DstReg, *RegRC, MRI)) { |
