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| author | Craig Topper <craig.topper@intel.com> | 2018-03-29 22:03:05 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-03-29 22:03:05 +0000 |
| commit | ee3c19fd7fb0d2fa8e2f7e49bd0bb7c1394fcda9 (patch) | |
| tree | 5c984e508b3ac250ccb1cc6e8d4900294311c875 /llvm/lib/Target/X86/X86InstrSSE.td | |
| parent | dd4baff48d3318b5bcd71e720050cb5696908083 (diff) | |
| download | bcm5719-llvm-ee3c19fd7fb0d2fa8e2f7e49bd0bb7c1394fcda9.tar.gz bcm5719-llvm-ee3c19fd7fb0d2fa8e2f7e49bd0bb7c1394fcda9.zip | |
[X86] Add ReadAfterLds to some 3 src instructions
Sometimes the operand comes after the memory operand so we need 5 ReadDefaults first.
I suspect we also need to do something for the mask operand for masked avx512 instructions? I'm not sure if the mask should be ReadAfterLd or not since it can mask faults. If it shouldn't be ReadAfterLd then we're probably wrong for zero masking instructions already.
Differential Revision: https://reviews.llvm.org/D44726
llvm-svn: 328834
Diffstat (limited to 'llvm/lib/Target/X86/X86InstrSSE.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSSE.td | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index 127509beab1..57b296a9671 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -6645,7 +6645,12 @@ multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr, (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)), RC:$src3))], itins.rm, SSEPackedInt>, TAPD, VEX_4V, - Sched<[itins.Sched.Folded, ReadAfterLd]>; + Sched<[itins.Sched.Folded, ReadAfterLd, + // x86memop:$src2 + ReadDefault, ReadDefault, ReadDefault, ReadDefault, + ReadDefault, + // RC::$src3 + ReadAfterLd]>; } let Predicates = [HasAVX] in { |
