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| author | Craig Topper <craig.topper@intel.com> | 2018-10-15 23:34:58 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-10-15 23:34:58 +0000 |
| commit | e70c560b6d2a6d5fc9cdaa6b3e6cb09a159e5f8b (patch) | |
| tree | 6c322319a282ff9ef8a2f178f85305e7a03c5705 /llvm/lib/Target/X86/X86InstrSSE.td | |
| parent | 079df9ab2cd137141d5444f994ecc9721a6e2b68 (diff) | |
| download | bcm5719-llvm-e70c560b6d2a6d5fc9cdaa6b3e6cb09a159e5f8b.tar.gz bcm5719-llvm-e70c560b6d2a6d5fc9cdaa6b3e6cb09a159e5f8b.zip | |
[X86] Remove some isel patterns that shouldn't be possible.
These included a bitcast of a load from v4f32 to v2f64, but DAG combine should have already changed the type of the load to remove the cast.
llvm-svn: 344573
Diffstat (limited to 'llvm/lib/Target/X86/X86InstrSSE.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSSE.td | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index b3c639f4f0c..8a836d8c173 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -265,8 +265,6 @@ let Predicates = [UseAVX] in { (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>; def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))), (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>; - def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))), - (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>; def : Pat<(v2f64 (X86vzload addr:$src)), (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>; @@ -349,8 +347,6 @@ let Predicates = [UseSSE2] in { (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>; def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))), (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>; - def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))), - (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>; def : Pat<(v2f64 (X86vzload addr:$src)), (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>; } |
