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| author | Craig Topper <craig.topper@intel.com> | 2019-01-30 19:57:01 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-01-30 19:57:01 +0000 |
| commit | 22b3de5b51f2d98252744217f45adaadeabec9da (patch) | |
| tree | 382575935396f75cf343f172747b67b66c391612 /llvm/lib/Target/X86/X86InstrMMX.td | |
| parent | e171ade25c9b7904f88ca8a370fcc7ced5671602 (diff) | |
| download | bcm5719-llvm-22b3de5b51f2d98252744217f45adaadeabec9da.tar.gz bcm5719-llvm-22b3de5b51f2d98252744217f45adaadeabec9da.zip | |
[X86] Mark EMMS and FEMMS as clobbering MM0-7 and ST0-7.
This fixes the test case in PR35982 by preventing MMX instructions that read MM0-7 from being moved below EMMS/FEMMS by the post RA scheduler.
Though as discussed in bugzilla, this is not a complete fix. There is still the possibility of reordering in IR or by the pre-RA scheduler.
Differential Revision: https://reviews.llvm.org/D57298
llvm-svn: 352660
Diffstat (limited to 'llvm/lib/Target/X86/X86InstrMMX.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrMMX.td | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86InstrMMX.td b/llvm/lib/Target/X86/X86InstrMMX.td index 8e2a45b1bed..57835b1a256 100644 --- a/llvm/lib/Target/X86/X86InstrMMX.td +++ b/llvm/lib/Target/X86/X86InstrMMX.td @@ -152,7 +152,9 @@ multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC, // MMX EMMS Instruction //===----------------------------------------------------------------------===// -let SchedRW = [WriteEMMS] in +let SchedRW = [WriteEMMS], + Defs = [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, + ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7] in def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms", [(int_x86_mmx_emms)]>; //===----------------------------------------------------------------------===// |
