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| author | Craig Topper <craig.topper@intel.com> | 2018-01-08 06:53:54 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-01-08 06:53:54 +0000 |
| commit | f090e8a89a9b58e462422ba730310bccfd052ee4 (patch) | |
| tree | da18c332740a6aa4c54d4132db4b22cb305bb293 /llvm/lib/Target/X86/X86InstrAVX512.td | |
| parent | a2018e799a716aaaef9ced091e79994255e0b161 (diff) | |
| download | bcm5719-llvm-f090e8a89a9b58e462422ba730310bccfd052ee4.tar.gz bcm5719-llvm-f090e8a89a9b58e462422ba730310bccfd052ee4.zip | |
[X86] Replace CVT2MASK ISD opcode with PCMPGTM compared to zero.
CVT2MASK is just checking the sign bit which can be represented with a comparison with zero.
llvm-svn: 321985
Diffstat (limited to 'llvm/lib/Target/X86/X86InstrAVX512.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index b7061bedcf1..e617a5d09de 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -8751,7 +8751,7 @@ defm VPMOVM2Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, "vpmovm2", HasDQI multiclass convert_vector_to_mask_common<bits<8> opc, X86VectorVTInfo _, string OpcodeStr > { def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.KRC:$dst), (ins _.RC:$src), !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), - [(set _.KRC:$dst, (X86cvt2mask (_.VT _.RC:$src)))], + [(set _.KRC:$dst, (X86pcmpgtm _.ImmAllZerosV, (_.VT _.RC:$src)))], IIC_SSE_MOV_S_RR>, EVEX, Sched<[WriteMove]>; } @@ -8759,7 +8759,7 @@ multiclass convert_vector_to_mask_common<bits<8> opc, X86VectorVTInfo _, string multiclass convert_vector_to_mask_lowering<X86VectorVTInfo ExtendInfo, X86VectorVTInfo _> { - def : Pat<(_.KVT (X86cvt2mask (_.VT _.RC:$src))), + def : Pat<(_.KVT (X86pcmpgtm _.ImmAllZerosV, (_.VT _.RC:$src))), (_.KVT (COPY_TO_REGCLASS (!cast<Instruction>(NAME#"Zrr") (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)), |
