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authorSaleem Abdulrasool <compnerd@compnerd.org>2014-06-29 21:43:47 +0000
committerSaleem Abdulrasool <compnerd@compnerd.org>2014-06-29 21:43:47 +0000
commit67b548154ea08dd9c0e3456c2d7c82803fe2d64b (patch)
treeeab169feada64590bdbe20542e633943ddd756a4 /llvm/lib/Target/X86/X86FrameLowering.cpp
parentf94e7d74f7c231151ab2c92882f585e625cd03f6 (diff)
downloadbcm5719-llvm-67b548154ea08dd9c0e3456c2d7c82803fe2d64b.tar.gz
bcm5719-llvm-67b548154ea08dd9c0e3456c2d7c82803fe2d64b.zip
CodeGen: rename Win64 ExceptionHandling to WinEH
This exception format is not specific to Windows x64. A similar approach is taken on nearly all architectures. Generalise the name to reflect reality. This will eventually be used for Windows on ARM data emission as well. Switch the enum and namespace into an enum class. llvm-svn: 212000
Diffstat (limited to 'llvm/lib/Target/X86/X86FrameLowering.cpp')
-rw-r--r--llvm/lib/Target/X86/X86FrameLowering.cpp16
1 files changed, 8 insertions, 8 deletions
diff --git a/llvm/lib/Target/X86/X86FrameLowering.cpp b/llvm/lib/Target/X86/X86FrameLowering.cpp
index 886ee1ef0e4..1544549e5e9 100644
--- a/llvm/lib/Target/X86/X86FrameLowering.cpp
+++ b/llvm/lib/Target/X86/X86FrameLowering.cpp
@@ -451,12 +451,12 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
bool Is64Bit = STI.is64Bit();
bool IsLP64 = STI.isTarget64BitLP64();
bool IsWin64 = STI.isTargetWin64();
- bool IsSEH =
+ bool IsWinEH =
MF.getTarget().getMCAsmInfo()->getExceptionHandlingType() ==
- ExceptionHandling::Win64; // Not necessarily synonymous with IsWin64.
- bool NeedsWin64SEH = IsSEH && Fn->needsUnwindTableEntry();
+ ExceptionHandling::WinEH; // Not necessarily synonymous with IsWin64.
+ bool NeedsWinEH = IsWinEH && Fn->needsUnwindTableEntry();
bool NeedsDwarfCFI =
- !IsSEH && (MMI.hasDebugInfo() || Fn->needsUnwindTableEntry());
+ !IsWinEH && (MMI.hasDebugInfo() || Fn->needsUnwindTableEntry());
bool UseLEA = STI.useLeaForSP();
unsigned StackAlign = getStackAlignment();
unsigned SlotSize = RegInfo->getSlotSize();
@@ -572,7 +572,7 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
.addCFIIndex(CFIIndex);
}
- if (NeedsWin64SEH) {
+ if (NeedsWinEH) {
BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
.addImm(FramePtr)
.setMIFlag(MachineInstr::FrameSetup);
@@ -623,7 +623,7 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
StackOffset += stackGrowth;
}
- if (NeedsWin64SEH) {
+ if (NeedsWinEH) {
BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg)).addImm(Reg).setMIFlag(
MachineInstr::FrameSetup);
}
@@ -735,7 +735,7 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
}
int SEHFrameOffset = 0;
- if (NeedsWin64SEH) {
+ if (NeedsWinEH) {
if (HasFP) {
// We need to set frame base offset low enough such that all saved
// register offsets would be positive relative to it, but we can't
@@ -775,7 +775,7 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
++MBBI;
// Emit SEH info for non-GPRs
- if (NeedsWin64SEH) {
+ if (NeedsWinEH) {
for (const CalleeSavedInfo &Info : MFI->getCalleeSavedInfo()) {
unsigned Reg = Info.getReg();
if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
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