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author | Craig Topper <craig.topper@intel.com> | 2019-04-05 19:27:49 +0000 |
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committer | Craig Topper <craig.topper@intel.com> | 2019-04-05 19:27:49 +0000 |
commit | 7323c2bf850b61b85252e17e6f1f73037c328378 (patch) | |
tree | bec1eabcb3f5ccd842c2e22472c5a9b90b7faff5 /llvm/lib/Target/X86/X86FixupSetCC.cpp | |
parent | e0bfeb5f24979416144c16e8b99204f5f163b889 (diff) | |
download | bcm5719-llvm-7323c2bf850b61b85252e17e6f1f73037c328378.tar.gz bcm5719-llvm-7323c2bf850b61b85252e17e6f1f73037c328378.zip |
[X86] Merge the different SETcc instructions for each condition code into single instructions that store the condition code as an operand.
Summary:
This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between SETcc instructions and condition codes.
Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.
Reviewers: andreadb, courbet, RKSimon, spatel, lebedev.ri
Reviewed By: andreadb
Subscribers: hiraditya, lebedev.ri, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60138
llvm-svn: 357801
Diffstat (limited to 'llvm/lib/Target/X86/X86FixupSetCC.cpp')
-rw-r--r-- | llvm/lib/Target/X86/X86FixupSetCC.cpp | 26 |
1 files changed, 1 insertions, 25 deletions
diff --git a/llvm/lib/Target/X86/X86FixupSetCC.cpp b/llvm/lib/Target/X86/X86FixupSetCC.cpp index 5bfad71ec05..e2d4d1ede6f 100644 --- a/llvm/lib/Target/X86/X86FixupSetCC.cpp +++ b/llvm/lib/Target/X86/X86FixupSetCC.cpp @@ -67,30 +67,6 @@ char X86FixupSetCCPass::ID = 0; FunctionPass *llvm::createX86FixupSetCC() { return new X86FixupSetCCPass(); } -bool X86FixupSetCCPass::isSetCCr(unsigned Opcode) { - switch (Opcode) { - default: - return false; - case X86::SETOr: - case X86::SETNOr: - case X86::SETBr: - case X86::SETAEr: - case X86::SETEr: - case X86::SETNEr: - case X86::SETBEr: - case X86::SETAr: - case X86::SETSr: - case X86::SETNSr: - case X86::SETPr: - case X86::SETNPr: - case X86::SETLr: - case X86::SETGEr: - case X86::SETLEr: - case X86::SETGr: - return true; - } -} - // We expect the instruction *immediately* before the setcc to imp-def // EFLAGS (because of scheduling glue). To make this less brittle w.r.t // scheduling, look backwards until we hit the beginning of the @@ -128,7 +104,7 @@ bool X86FixupSetCCPass::runOnMachineFunction(MachineFunction &MF) { // Find a setcc that is used by a zext. // This doesn't have to be the only use, the transformation is safe // regardless. - if (!isSetCCr(MI.getOpcode())) + if (MI.getOpcode() != X86::SETCCr) continue; MachineInstr *ZExt = nullptr; |