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| author | Craig Topper <craig.topper@intel.com> | 2019-05-11 16:00:28 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-05-11 16:00:28 +0000 |
| commit | c9d7484aa36e974a265b88dfbaa75cf8ea7cd5bc (patch) | |
| tree | 46d07f0ed9fef99682f4f1d9c36800a316a08976 /llvm/lib/Target/X86/X86FastISel.cpp | |
| parent | 74a436596d7381eed99bccca6037e0d698647eda (diff) | |
| download | bcm5719-llvm-c9d7484aa36e974a265b88dfbaa75cf8ea7cd5bc.tar.gz bcm5719-llvm-c9d7484aa36e974a265b88dfbaa75cf8ea7cd5bc.zip | |
[X86] Add CMOV_FR32X/CMOV_FR64X pseudo instructions. Use them in fast isel to fix a machine verifier error after adding test cases.
Fast isel picks the FR32X/FR64X register classes when lowering pseudo select, but it didn't have the right opcode to go with it.
llvm-svn: 360524
Diffstat (limited to 'llvm/lib/Target/X86/X86FastISel.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86FastISel.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp index e9202a654ff..c397d7046c3 100644 --- a/llvm/lib/Target/X86/X86FastISel.cpp +++ b/llvm/lib/Target/X86/X86FastISel.cpp @@ -2281,8 +2281,10 @@ bool X86FastISel::X86FastEmitPseudoSelect(MVT RetVT, const Instruction *I) { case MVT::i8: Opc = X86::CMOV_GR8; break; case MVT::i16: Opc = X86::CMOV_GR16; break; case MVT::i32: Opc = X86::CMOV_GR32; break; - case MVT::f32: Opc = X86::CMOV_FR32; break; - case MVT::f64: Opc = X86::CMOV_FR64; break; + case MVT::f32: Opc = Subtarget->hasAVX512() ? X86::CMOV_FR32X + : X86::CMOV_FR32; break; + case MVT::f64: Opc = Subtarget->hasAVX512() ? X86::CMOV_FR64X + : X86::CMOV_FR64; break; } const Value *Cond = I->getOperand(0); |
