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| author | Benjamin Kramer <benny.kra@googlemail.com> | 2010-01-05 20:07:06 +0000 |
|---|---|---|
| committer | Benjamin Kramer <benny.kra@googlemail.com> | 2010-01-05 20:07:06 +0000 |
| commit | a81a6dff0d7748f05637ac07a6da7a150094c88f (patch) | |
| tree | 1b3a270ef2188a38b14c94ad5c724dc369b84cbc /llvm/lib/Target/X86/X86FastISel.cpp | |
| parent | 76aa677ec348ce6e88a5af977b135a05799419d4 (diff) | |
| download | bcm5719-llvm-a81a6dff0d7748f05637ac07a6da7a150094c88f.tar.gz bcm5719-llvm-a81a6dff0d7748f05637ac07a6da7a150094c88f.zip | |
Convert a ton of simple integer type equality tests to the new predicate.
llvm-svn: 92760
Diffstat (limited to 'llvm/lib/Target/X86/X86FastISel.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86FastISel.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp index 431c120f8f0..10fba2461ed 100644 --- a/llvm/lib/Target/X86/X86FastISel.cpp +++ b/llvm/lib/Target/X86/X86FastISel.cpp @@ -786,8 +786,8 @@ bool X86FastISel::X86SelectCmp(Instruction *I) { bool X86FastISel::X86SelectZExt(Instruction *I) { // Handle zero-extension from i1 to i8, which is common. - if (I->getType() == Type::getInt8Ty(I->getContext()) && - I->getOperand(0)->getType() == Type::getInt1Ty(I->getContext())) { + if (I->getType()->isInteger(8) && + I->getOperand(0)->getType()->isInteger(1)) { unsigned ResultReg = getRegForValue(I->getOperand(0)); if (ResultReg == 0) return false; // Set the high bits to zero. @@ -948,7 +948,7 @@ bool X86FastISel::X86SelectBranch(Instruction *I) { bool X86FastISel::X86SelectShift(Instruction *I) { unsigned CReg = 0, OpReg = 0, OpImm = 0; const TargetRegisterClass *RC = NULL; - if (I->getType() == Type::getInt8Ty(I->getContext())) { + if (I->getType()->isInteger(8)) { CReg = X86::CL; RC = &X86::GR8RegClass; switch (I->getOpcode()) { @@ -957,7 +957,7 @@ bool X86FastISel::X86SelectShift(Instruction *I) { case Instruction::Shl: OpReg = X86::SHL8rCL; OpImm = X86::SHL8ri; break; default: return false; } - } else if (I->getType() == Type::getInt16Ty(I->getContext())) { + } else if (I->getType()->isInteger(16)) { CReg = X86::CX; RC = &X86::GR16RegClass; switch (I->getOpcode()) { @@ -966,7 +966,7 @@ bool X86FastISel::X86SelectShift(Instruction *I) { case Instruction::Shl: OpReg = X86::SHL16rCL; OpImm = X86::SHL16ri; break; default: return false; } - } else if (I->getType() == Type::getInt32Ty(I->getContext())) { + } else if (I->getType()->isInteger(32)) { CReg = X86::ECX; RC = &X86::GR32RegClass; switch (I->getOpcode()) { @@ -975,7 +975,7 @@ bool X86FastISel::X86SelectShift(Instruction *I) { case Instruction::Shl: OpReg = X86::SHL32rCL; OpImm = X86::SHL32ri; break; default: return false; } - } else if (I->getType() == Type::getInt64Ty(I->getContext())) { + } else if (I->getType()->isInteger(64)) { CReg = X86::RCX; RC = &X86::GR64RegClass; switch (I->getOpcode()) { |
