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authorCraig Topper <craig.topper@intel.com>2019-01-10 07:43:54 +0000
committerCraig Topper <craig.topper@intel.com>2019-01-10 07:43:54 +0000
commit5d20eb240fd8f89bdf774eb94cac8c3ff1fceab3 (patch)
treecd30be4a8e9ee65a2dd193d7e24d458e4a32418f /llvm/lib/Target/X86/X86DomainReassignment.cpp
parent64c956eea855503b1b16dba3cdd0956f5528e0db (diff)
downloadbcm5719-llvm-5d20eb240fd8f89bdf774eb94cac8c3ff1fceab3.tar.gz
bcm5719-llvm-5d20eb240fd8f89bdf774eb94cac8c3ff1fceab3.zip
[X86] Disable DomainReassignment pass when AVX512BW is disabled to avoid injecting VK32/VK64 references into the MachineIR
Summary: This pass replaces GR8/GR16/GR32/GR64 with their equivalent sized mask register classes. But VK32/VK64 aren't legal without AVX512BW. Apparently this mostly appears to work if the register coalescer is able to remove the VK32/VK64 register class reference. Or if we don't ever spill it. But there's no guarantee of that. Another Intel employee managed to trigger a crash due to this with ISPC. Unfortunately, I've lost the test case he sent me at the time. I'm trying to get him to reproduce it for me. I'd like to get this in before 8.0 branches since its a little scary. The regressions here are unfortunate, but I think we can make some improvements to DAG combine, load folding, etc. to fix them. Just not sure if we can get that done for 8.0. Fixes PR39741 Reviewers: RKSimon, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D56460 llvm-svn: 350800
Diffstat (limited to 'llvm/lib/Target/X86/X86DomainReassignment.cpp')
-rw-r--r--llvm/lib/Target/X86/X86DomainReassignment.cpp5
1 files changed, 4 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86DomainReassignment.cpp b/llvm/lib/Target/X86/X86DomainReassignment.cpp
index 7e1f1e7876c..d9ebbb506ca 100644
--- a/llvm/lib/Target/X86/X86DomainReassignment.cpp
+++ b/llvm/lib/Target/X86/X86DomainReassignment.cpp
@@ -732,7 +732,10 @@ bool X86DomainReassignment::runOnMachineFunction(MachineFunction &MF) {
STI = &MF.getSubtarget<X86Subtarget>();
// GPR->K is the only transformation currently supported, bail out early if no
// AVX512.
- if (!STI->hasAVX512())
+ // TODO: We're also bailing of AVX512BW isn't supported since we use VK32 and
+ // VK64 for GR32/GR64, but those aren't legal classes on KNL. If the register
+ // coalescer doesn't clean it up and we generate a spill we will crash.
+ if (!STI->hasAVX512() || !STI->hasBWI())
return false;
MRI = &MF.getRegInfo();
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