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| author | Oren Ben Simhon <oren.ben.simhon@intel.com> | 2016-11-17 09:59:40 +0000 |
|---|---|---|
| committer | Oren Ben Simhon <oren.ben.simhon@intel.com> | 2016-11-17 09:59:40 +0000 |
| commit | 489d6eff4fecd00aa2a384dbe1991251b1175a01 (patch) | |
| tree | 1dfdcca75f40a02363028b5afe97567889e06a3b /llvm/lib/Target/X86/X86CallingConv.h | |
| parent | 9230db94b7b5c6b370fe7c297db79a3128fd4637 (diff) | |
| download | bcm5719-llvm-489d6eff4fecd00aa2a384dbe1991251b1175a01.tar.gz bcm5719-llvm-489d6eff4fecd00aa2a384dbe1991251b1175a01.zip | |
[X86] RegCall - Handling v64i1 in 32/64 bit target
Register Calling Convention defines a new behavior for v64i1 types.
This type should be saved in GPR.
However for 32 bit machine we need to split the value into 2 GPRs (because each is 32 bit).
Differential Revision: https://reviews.llvm.org/D26181
llvm-svn: 287217
Diffstat (limited to 'llvm/lib/Target/X86/X86CallingConv.h')
| -rw-r--r-- | llvm/lib/Target/X86/X86CallingConv.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86CallingConv.h b/llvm/lib/Target/X86/X86CallingConv.h index 39f442c2ea6..41fbd2e4474 100644 --- a/llvm/lib/Target/X86/X86CallingConv.h +++ b/llvm/lib/Target/X86/X86CallingConv.h @@ -21,6 +21,14 @@ namespace llvm { +/// When regcall calling convention compiled to 32 bit arch, special treatment +/// is required for 64 bit masks. +/// The value should be assigned to two GPRs. +/// @return true if registers were allocated and false otherwise +bool CC_X86_32_RegCall_Assign2Regs(unsigned &ValNo, MVT &ValVT, MVT &LocVT, + CCValAssign::LocInfo &LocInfo, + ISD::ArgFlagsTy &ArgFlags, CCState &State); + inline bool CC_X86_32_VectorCallIndirect(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, |
