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authorOren Ben Simhon <oren.ben.simhon@intel.com>2016-12-21 08:59:42 +0000
committerOren Ben Simhon <oren.ben.simhon@intel.com>2016-12-21 08:59:42 +0000
commitde2eea72987731ff0fcb504d9dc8c09d35b1178a (patch)
tree56793f4b2f05606198dfa061b29ca205b2455c26 /llvm/lib/Target/X86/X86CallingConv.cpp
parentcc9302d0b778709cdcd0b006c19ae968921bef3b (diff)
downloadbcm5719-llvm-de2eea72987731ff0fcb504d9dc8c09d35b1178a.tar.gz
bcm5719-llvm-de2eea72987731ff0fcb504d9dc8c09d35b1178a.zip
[X86] Vectorcall Calling Convention - Adding CodeGen Complete Support
Fixing build issues. llvm-svn: 290244
Diffstat (limited to 'llvm/lib/Target/X86/X86CallingConv.cpp')
-rw-r--r--llvm/lib/Target/X86/X86CallingConv.cpp8
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86CallingConv.cpp b/llvm/lib/Target/X86/X86CallingConv.cpp
index ae3f5b58b5f..c96e76bc7a4 100644
--- a/llvm/lib/Target/X86/X86CallingConv.cpp
+++ b/llvm/lib/Target/X86/X86CallingConv.cpp
@@ -62,23 +62,23 @@ static ArrayRef<MCPhysReg> CC_X86_VectorCallGetSSEs(const MVT &ValVT) {
if (ValVT.is512BitVector()) {
static const MCPhysReg RegListZMM[] = {X86::ZMM0, X86::ZMM1, X86::ZMM2,
X86::ZMM3, X86::ZMM4, X86::ZMM5};
- return RegListZMM;
+ return makeArrayRef(std::begin(RegListZMM), std::end(RegListZMM));
}
if (ValVT.is256BitVector()) {
static const MCPhysReg RegListYMM[] = {X86::YMM0, X86::YMM1, X86::YMM2,
X86::YMM3, X86::YMM4, X86::YMM5};
- return RegListYMM;
+ return makeArrayRef(std::begin(RegListYMM), std::end(RegListYMM));
}
static const MCPhysReg RegListXMM[] = {X86::XMM0, X86::XMM1, X86::XMM2,
X86::XMM3, X86::XMM4, X86::XMM5};
- return RegListXMM;
+ return makeArrayRef(std::begin(RegListXMM), std::end(RegListXMM));
}
static ArrayRef<MCPhysReg> CC_X86_64_VectorCallGetGPRs() {
static const MCPhysReg RegListGPR[] = {X86::RCX, X86::RDX, X86::R8, X86::R9};
- return RegListGPR;
+ return makeArrayRef(std::begin(RegListGPR), std::end(RegListGPR));
}
static bool CC_X86_VectorCallAssignRegister(unsigned &ValNo, MVT &ValVT,
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