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authorAlexey Volkov <avolkov.intel@gmail.com>2014-05-20 08:55:50 +0000
committerAlexey Volkov <avolkov.intel@gmail.com>2014-05-20 08:55:50 +0000
commit6226de67210755a56d15dca7f1891fe7fddda3ca (patch)
tree49e5679bb8c10b7fed4057f8b74aecbf2b818d01 /llvm/lib/Target/X86/X86.td
parentabdf44e7f38d392fed85692b2a31bf1578f3ee3b (diff)
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[X86] Tune LEA usage for Silvermont
According to Intel Software Optimization Manual on Silvermont in some cases LEA is better to be replaced with ADD instructions: "The rule of thumb for ADDs and LEAs is that it is justified to use LEA with a valid index and/or displacement for non-destructive destination purposes (especially useful for stack offset cases), or to use a SCALE. Otherwise, ADD(s) are preferable." Differential Revision: http://reviews.llvm.org/D3826 llvm-svn: 209198
Diffstat (limited to 'llvm/lib/Target/X86/X86.td')
-rw-r--r--llvm/lib/Target/X86/X86.td3
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index d01e4621616..6912b579b12 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -166,6 +166,8 @@ def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
"Call register indirect">;
def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
"LEA instruction needs inputs at AG stage">;
+def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
+ "LEA instruction with certain arguments is slow">;
//===----------------------------------------------------------------------===//
// X86 processors supported.
@@ -226,6 +228,7 @@ def : ProcessorModel<"slm", SLMModel, [ProcIntelSLM,
FeaturePCLMUL, FeatureAES,
FeatureCallRegIndirect,
FeaturePRFCHW,
+ FeatureSlowLEA,
FeatureSlowBTMem, FeatureFastUAMem]>;
// "Arrandale" along with corei3 and corei5
def : ProcessorModel<"corei7", SandyBridgeModel,
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