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authorCraig Topper <craig.topper@intel.com>2019-04-01 19:08:15 +0000
committerCraig Topper <craig.topper@intel.com>2019-04-01 19:08:15 +0000
commit4307172b8413fd40a63cd9adf54973e641a891ba (patch)
treee12d1d74c061a1f66fe8bbf8307d7d744bf7afef /llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
parentf2baddb0fc48708ce1deb1428c89dd3504636f18 (diff)
downloadbcm5719-llvm-4307172b8413fd40a63cd9adf54973e641a891ba.tar.gz
bcm5719-llvm-4307172b8413fd40a63cd9adf54973e641a891ba.zip
[X86] Classify the AVX512 rounding control operand as X86::OPERAND_ROUNDING_CONTROL instead of MCOI::OPERAND_IMMEDIATE. Add an assert on legal values of rounding control in the encoder and remove an explicit mask.
This should allow llvm-exegesis to intelligently constrain the rounding mode. The mask in the encoder shouldn't be necessary any more. We used to allow codegen to use 8-11 for rounding mode and the assembler would use 0-3 to mean the same thing so we masked here and in the printer. Codegen now matches the assembler and the printer was updated, but I forgot to update the encoder. llvm-svn: 357419
Diffstat (limited to 'llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp')
-rw-r--r--llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
index fd95387b076..353f52a8c20 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
@@ -879,7 +879,8 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
if (HasEVEX_RC) {
unsigned RcOperand = NumOps-1;
assert(RcOperand >= CurOp);
- EVEX_rc = MI.getOperand(RcOperand).getImm() & 0x3;
+ EVEX_rc = MI.getOperand(RcOperand).getImm();
+ assert(EVEX_rc <= 3 && "Invalid rounding control!");
}
EncodeRC = true;
}
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