Now that compare instructions aren't lumped in with the other twoargfp instructions,

we can get rid of the FpUCOM/FpUCOMi pseudo instructions, which makes stuff simpler
and faster.

llvm-svn: 14144

1 files changed, 4 insertions, 4 deletions

diff --git a/llvm/lib/Target/X86/InstSelectSimple.cpp b/llvm/lib/Target/X86/InstSelectSimple.cpp
index 1adcd52c2e3..7ed3452278a 100644
--- a/llvm/lib/Target/X86/InstSelectSimple.cpp
+++ b/llvm/lib/Target/X86/InstSelectSimple.cpp
@@ -1005,11 +1005,11 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
     break;
   case cFP:
     if (0) { // for processors prior to the P6
-      BuildMI(*MBB, IP, X86::FpUCOM, 2).addReg(Op0r).addReg(Op1r);
+      BuildMI(*MBB, IP, X86::FUCOMr, 2).addReg(Op0r).addReg(Op1r);
       BuildMI(*MBB, IP, X86::FNSTSW8r, 0);
       BuildMI(*MBB, IP, X86::SAHF, 1);
     } else {
-      BuildMI(*MBB, IP, X86::FpUCOMI, 2).addReg(Op0r).addReg(Op1r);
+      BuildMI(*MBB, IP, X86::FUCOMIr, 2).addReg(Op0r).addReg(Op1r);
     }
     break;
 
@@ -1701,11 +1701,11 @@ void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
   case Intrinsic::isnan:
     TmpReg1 = getReg(CI.getOperand(1));
     if (0) { // for processors prior to the P6
-      BuildMI(BB, X86::FpUCOM, 2).addReg(TmpReg1).addReg(TmpReg1);
+      BuildMI(BB, X86::FUCOMr, 2).addReg(TmpReg1).addReg(TmpReg1);
       BuildMI(BB, X86::FNSTSW8r, 0);
       BuildMI(BB, X86::SAHF, 1);
     } else {
-      BuildMI(BB, X86::FpUCOMI, 2).addReg(TmpReg1).addReg(TmpReg1);
+      BuildMI(BB, X86::FUCOMIr, 2).addReg(TmpReg1).addReg(TmpReg1);
     }
     TmpReg2 = getReg(CI);
     BuildMI(BB, X86::SETPr, 0, TmpReg2);