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authorCraig Topper <craig.topper@gmail.com>2014-01-16 07:36:58 +0000
committerCraig Topper <craig.topper@gmail.com>2014-01-16 07:36:58 +0000
commit35da3d190accbc031c50af740af750cd8c129136 (patch)
treebd5b426e2b6e1c535bad197f851d0ae41ce41727 /llvm/lib/Target/X86/InstPrinter
parent74c3e6319328afe8ecb2b96e6c3961fa26520cf5 (diff)
downloadbcm5719-llvm-35da3d190accbc031c50af740af750cd8c129136.tar.gz
bcm5719-llvm-35da3d190accbc031c50af740af750cd8c129136.zip
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962.
llvm-svn: 199364
Diffstat (limited to 'llvm/lib/Target/X86/InstPrinter')
-rw-r--r--llvm/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp7
-rw-r--r--llvm/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp7
2 files changed, 14 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp b/llvm/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
index 8c2bb0f9e9f..11a9ada41e5 100644
--- a/llvm/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
+++ b/llvm/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
@@ -229,9 +229,16 @@ void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
void X86ATTInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
raw_ostream &O) {
const MCOperand &DispSpec = MI->getOperand(Op);
+ const MCOperand &SegReg = MI->getOperand(Op+1);
O << markup("<mem:");
+ // If this has a segment register, print it.
+ if (SegReg.getReg()) {
+ printOperand(MI, Op+1, O);
+ O << ':';
+ }
+
if (DispSpec.isImm()) {
O << formatImm(DispSpec.getImm());
} else {
diff --git a/llvm/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp b/llvm/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp
index 7255d560cca..59634f9ad85 100644
--- a/llvm/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp
+++ b/llvm/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp
@@ -215,6 +215,13 @@ void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
raw_ostream &O) {
const MCOperand &DispSpec = MI->getOperand(Op);
+ const MCOperand &SegReg = MI->getOperand(Op+1);
+
+ // If this has a segment register, print it.
+ if (SegReg.getReg()) {
+ printOperand(MI, Op+1, O);
+ O << ':';
+ }
O << '[';
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