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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-08-06 03:59:31 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-08-06 03:59:31 +0000 |
| commit | f4d3113a5fd6ac09dc5498bbbdfecc7d8e336951 (patch) | |
| tree | 270e8cd714097bf8bfb5a449750eca9348934751 /llvm/lib/Target/WebAssembly | |
| parent | acd0a53c02bcad5748dcac9ae25842ea5d564341 (diff) | |
| download | bcm5719-llvm-f4d3113a5fd6ac09dc5498bbbdfecc7d8e336951.tar.gz bcm5719-llvm-f4d3113a5fd6ac09dc5498bbbdfecc7d8e336951.zip | |
CodeGen: Migration to using Register
llvm-svn: 367974
Diffstat (limited to 'llvm/lib/Target/WebAssembly')
| -rw-r--r-- | llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp index 2552e915083..48d19c0893b 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp @@ -1141,14 +1141,14 @@ bool WebAssemblyFastISel::selectBitCast(const Instruction *I) { return true; } - unsigned Reg = fastEmit_ISD_BITCAST_r(VT.getSimpleVT(), RetVT.getSimpleVT(), + Register Reg = fastEmit_ISD_BITCAST_r(VT.getSimpleVT(), RetVT.getSimpleVT(), In, I->getOperand(0)->hasOneUse()); if (!Reg) return false; MachineBasicBlock::iterator Iter = FuncInfo.InsertPt; --Iter; assert(Iter->isBitcast()); - Iter->setPhysRegsDeadExcept(ArrayRef<unsigned>(), TRI); + Iter->setPhysRegsDeadExcept(ArrayRef<Register>(), TRI); updateValueMap(I, Reg); return true; } |
