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| author | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2018-03-02 20:51:59 +0000 |
|---|---|---|
| committer | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2018-03-02 20:51:59 +0000 |
| commit | db16beed8a8fa79554942f206b8077ae2e91195d (patch) | |
| tree | 0829fd50352b62d1fc2297e22f8efc4bb30de564 /llvm/lib/Target/WebAssembly | |
| parent | 8b19be46c770754cbeb4c8990c2cae0773203904 (diff) | |
| download | bcm5719-llvm-db16beed8a8fa79554942f206b8077ae2e91195d.tar.gz bcm5719-llvm-db16beed8a8fa79554942f206b8077ae2e91195d.zip | |
[SystemZ] Allow LRV/STRV with volatile memory accesses
The byte-swapping loads and stores do not actually perform multiple
accesses to their memory operand, so they are OK to use with volatile
memory operands as well. Remove overly cautious check.
llvm-svn: 326613
Diffstat (limited to 'llvm/lib/Target/WebAssembly')
0 files changed, 0 insertions, 0 deletions
