[WebAssembly] Add sign extend instructions from atomics proposal

Select them from ISD::SIGN_EXTEND_INREG

Differential Revision: https://reviews.llvm.org/D37603

remove spurious change

llvm-svn: 313101

2 files changed, 24 insertions, 2 deletions

diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index 5615ec184d7..91db3da0926 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -115,8 +115,12 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
 
   // As a special case, these operators use the type to mean the type to
   // sign-extend from.
-  for (auto T : {MVT::i1, MVT::i8, MVT::i16, MVT::i32})
-    setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand);
+  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
+  if (!Subtarget->hasAtomics()) {
+    // The Atomics feature includes signext intructions.
+    for (auto T : {MVT::i8, MVT::i16, MVT::i32})
+      setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand);
+  }
 
   // Dynamic stack allocation: use the default expansion.
   setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrConv.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrConv.td
index 29483ba663d..d2decb23e2b 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrConv.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrConv.td
@@ -26,6 +26,24 @@ def I64_EXTEND_U_I32 : I<(outs I64:$dst), (ins I32:$src),
                          [(set I64:$dst, (zext I32:$src))],
                          "i64.extend_u/i32\t$dst, $src", 0xad>;
 
+let Predicates = [HasAtomics] in {
+def I32_EXTEND8_S_I32 : I<(outs I32:$dst), (ins I32:$src),
+                          [(set I32:$dst, (sext_inreg I32:$src, i8))],
+                          "i32.extend8_s\t$dst, $src", 0xc0>;
+def I32_EXTEND16_S_I32 : I<(outs I32:$dst), (ins I32:$src),
+                           [(set I32:$dst, (sext_inreg I32:$src, i16))],
+                           "i32.extend16_s\t$dst, $src", 0xc1>;
+def I64_EXTEND8_S_I64 : I<(outs I64:$dst), (ins I64:$src),
+                           [(set I64:$dst, (sext_inreg I64:$src, i8))],
+                           "i64.extend8_s\t$dst, $src", 0xc2>;
+def I64_EXTEND16_S_I64 : I<(outs I64:$dst), (ins I64:$src),
+                           [(set I64:$dst, (sext_inreg I64:$src, i16))],
+                           "i64.extend16_s\t$dst, $src", 0xc3>;
+def I64_EXTEND32_S_I64 : I<(outs I64:$dst), (ins I64:$src),
+                           [(set I64:$dst, (sext_inreg I64:$src, i32))],
+                           "i64.extend32_s\t$dst, $src", 0xc4>;
+} // Predicates = [HasAtomics]
+
 } // defs = [ARGUMENTS]
 
 // Expand a "don't care" extend into zero-extend (chosen over sign-extend