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author | Dan Gohman <dan433584@gmail.com> | 2016-05-16 18:59:34 +0000 |
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committer | Dan Gohman <dan433584@gmail.com> | 2016-05-16 18:59:34 +0000 |
commit | 804749c942fa15d6f0f0e6fde2ad7407e8bedb8b (patch) | |
tree | 1613d19feb4e2bfba44ed00c37b021a6ebbd66bb /llvm/lib/Target/WebAssembly | |
parent | bf05a4589e28521d7a43bd4068aaf426979987cc (diff) | |
download | bcm5719-llvm-804749c942fa15d6f0f0e6fde2ad7407e8bedb8b.tar.gz bcm5719-llvm-804749c942fa15d6f0f0e6fde2ad7407e8bedb8b.zip |
[WebAssembly] Use eqz to negate a branch conditions.
llvm-svn: 269681
Diffstat (limited to 'llvm/lib/Target/WebAssembly')
-rw-r--r-- | llvm/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp | 10 |
1 files changed, 2 insertions, 8 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp index 201c5ab0bc1..af53f3db967 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp @@ -106,16 +106,10 @@ bool WebAssemblyLowerBrUnless::runOnMachineFunction(MachineFunction &MF) { // If we weren't able to invert the condition in place. Insert an // expression to invert it. if (!Inverted) { - unsigned ZeroReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass); - MFI.stackifyVReg(ZeroReg); - BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::CONST_I32), - ZeroReg) - .addImm(0); unsigned Tmp = MRI.createVirtualRegister(&WebAssembly::I32RegClass); MFI.stackifyVReg(Tmp); - BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::EQ_I32), Tmp) - .addReg(Cond) - .addReg(ZeroReg); + BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::EQZ_I32), Tmp) + .addReg(Cond); Cond = Tmp; Inverted = true; } |