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| author | Dan Gohman <dan433584@gmail.com> | 2015-11-13 00:46:31 +0000 |
|---|---|---|
| committer | Dan Gohman <dan433584@gmail.com> | 2015-11-13 00:46:31 +0000 |
| commit | 231244c304f4a49ccb63493302a8876a2672be69 (patch) | |
| tree | e282ca7f068cb4b029d6352ea4e07b1ab950ed9c /llvm/lib/Target/WebAssembly | |
| parent | 7828b1e604f22e81815a3c2fc357e319f2807bb8 (diff) | |
| download | bcm5719-llvm-231244c304f4a49ccb63493302a8876a2672be69.tar.gz bcm5719-llvm-231244c304f4a49ccb63493302a8876a2672be69.zip | |
[WebAssembly] Rename BR_IF_ to BR_IF
With MC-based instruction printing, we no longer need instruction names to
mangle in hints about how they should be printed.
llvm-svn: 252987
Diffstat (limited to 'llvm/lib/Target/WebAssembly')
| -rw-r--r-- | llvm/lib/Target/WebAssembly/WebAssemblyISD.def | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp | 4 |
3 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISD.def b/llvm/lib/Target/WebAssembly/WebAssemblyISD.def index 36b6d9c68c8..52c37757cdb 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyISD.def +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISD.def @@ -19,7 +19,7 @@ HANDLE_NODETYPE(CALL0) HANDLE_NODETYPE(RETURN) HANDLE_NODETYPE(ARGUMENT) HANDLE_NODETYPE(Wrapper) -HANDLE_NODETYPE(BR_IF_) +HANDLE_NODETYPE(BR_IF) HANDLE_NODETYPE(SWITCH) // add memory opcodes starting at ISD::FIRST_TARGET_MEMORY_OPCODE here... diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td index b5140324d4f..5883553e8f1 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td @@ -13,9 +13,9 @@ //===----------------------------------------------------------------------===// let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in { -def BR_IF_ : I<(outs), (ins bb_op:$dst, I32:$a), - [(brcond I32:$a, bb:$dst)], - "br_if $dst, $a">; +def BR_IF : I<(outs), (ins bb_op:$dst, I32:$a), + [(brcond I32:$a, bb:$dst)], + "br_if $dst, $a">; let isBarrier = 1 in { def BR : I<(outs), (ins bb_op:$dst), [(br bb:$dst)], diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp index a18357da19e..fe27b1ac669 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp @@ -51,7 +51,7 @@ bool WebAssemblyInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, default: // Unhandled instruction; bail out. return true; - case WebAssembly::BR_IF_: + case WebAssembly::BR_IF: if (HaveCond) return true; Cond.push_back(MI.getOperand(1)); @@ -104,7 +104,7 @@ unsigned WebAssemblyInstrInfo::InsertBranch( return 1; } - BuildMI(&MBB, DL, get(WebAssembly::BR_IF_)) + BuildMI(&MBB, DL, get(WebAssembly::BR_IF)) .addMBB(TBB) .addOperand(Cond[0]); if (!FBB) |
