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authorDan Gohman <dan433584@gmail.com>2015-09-26 01:09:44 +0000
committerDan Gohman <dan433584@gmail.com>2015-09-26 01:09:44 +0000
commitd0bf981296b8d57b95f8d0c9680925612b7373a2 (patch)
tree49a19b4fdeb0c1cb990b9f65fdb8680004fd255d /llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td
parent6993ba4d3ec432b661b99111d2bf55da6379e3d5 (diff)
downloadbcm5719-llvm-d0bf981296b8d57b95f8d0c9680925612b7373a2.tar.gz
bcm5719-llvm-d0bf981296b8d57b95f8d0c9680925612b7373a2.zip
[WebAssembly] Rename several functions and types according to the new spec.
llvm-svn: 248644
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td')
-rw-r--r--llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td8
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td b/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td
index 2ba42eb94a4..2402bc52ed2 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td
@@ -48,7 +48,7 @@ foreach i = 0-4 in {
// Register classes
//===----------------------------------------------------------------------===//
-def Int32 : WebAssemblyRegClass<[i32], 32, (add (sequence "I%u", 0, 4), SP32)>;
-def Int64 : WebAssemblyRegClass<[i64], 64, (add (sequence "L%u", 0, 4), SP64)>;
-def Float32 : WebAssemblyRegClass<[f32], 32, (add (sequence "F%u", 0, 4))>;
-def Float64 : WebAssemblyRegClass<[f64], 64, (add (sequence "D%u", 0, 4))>;
+def I32 : WebAssemblyRegClass<[i32], 32, (add (sequence "I%u", 0, 4), SP32)>;
+def I64 : WebAssemblyRegClass<[i64], 64, (add (sequence "L%u", 0, 4), SP64)>;
+def F32 : WebAssemblyRegClass<[f32], 32, (add (sequence "F%u", 0, 4))>;
+def F64 : WebAssemblyRegClass<[f64], 64, (add (sequence "D%u", 0, 4))>;
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