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| author | Derek Schuff <dschuff@google.com> | 2016-08-02 23:16:09 +0000 |
|---|---|---|
| committer | Derek Schuff <dschuff@google.com> | 2016-08-02 23:16:09 +0000 |
| commit | 39bf39f35c208109f6d5907708ee53dee2878bed (patch) | |
| tree | 92c88047132b9387bfac686662ba7d8a3b9e0abc /llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td | |
| parent | 02a1e973a80adce224cd950bb2b5b2c78622829a (diff) | |
| download | bcm5719-llvm-39bf39f35c208109f6d5907708ee53dee2878bed.tar.gz bcm5719-llvm-39bf39f35c208109f6d5907708ee53dee2878bed.zip | |
[WebAssembly] Initial SIMD128 support.
Kicks off the implementation of wasm SIMD128 support (spec:
https://github.com/stoklund/portable-simd/blob/master/portable-simd.md),
adding support for add, sub, mul for i8x16, i16x8, i32x4, and f32x4.
The spec is WIP, and might change in the near future.
Patch by João Porto
Differential Revision: https://reviews.llvm.org/D22686
llvm-svn: 277543
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td')
| -rw-r--r-- | llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td b/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td index 80a83fa76b5..52456aac0b7 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td @@ -39,6 +39,8 @@ def SP64 : WebAssemblyReg<"%SP64">; def F32_0 : WebAssemblyReg<"%f32.0">; def F64_0 : WebAssemblyReg<"%f64.0">; +def V128_0: WebAssemblyReg<"%v128">; + // The expression stack "register". This is an opaque entity which serves to // order uses and defs that must remain in LIFO order. def EXPR_STACK : WebAssemblyReg<"STACK">; @@ -56,3 +58,5 @@ def I32 : WebAssemblyRegClass<[i32], 32, (add FP32, SP32)>; def I64 : WebAssemblyRegClass<[i64], 64, (add FP64, SP64)>; def F32 : WebAssemblyRegClass<[f32], 32, (add F32_0)>; def F64 : WebAssemblyRegClass<[f64], 64, (add F64_0)>; +def V128 : WebAssemblyRegClass<[v4f32, v4i32, v16i8, v8i16], 128, (add V128_0)>; + |
