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| author | Peter Smith <peter.smith@linaro.org> | 2019-06-04 16:35:40 +0000 |
|---|---|---|
| committer | Peter Smith <peter.smith@linaro.org> | 2019-06-04 16:35:40 +0000 |
| commit | f15e3d856fddd3ecf80fdbb798be64d0c4bc6de4 (patch) | |
| tree | c338e1a3c426cd555f6f6df4180d476c16e275cf /llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td | |
| parent | 8e8ddaa38ff691b4dd21a93bcc348a383f7ffcac (diff) | |
| download | bcm5719-llvm-f15e3d856fddd3ecf80fdbb798be64d0c4bc6de4.tar.gz bcm5719-llvm-f15e3d856fddd3ecf80fdbb798be64d0c4bc6de4.zip | |
[AArch64][ELF] Add support for PLT decoding with BTI instructions present
Arm Architecture v8.5a introduces Branch Target Identification (BTI). When
enabled all indirect branches must target a bti instruction of the
appropriate form. As PLT sequences may sometimes be the target of an
indirect branch and PLT[0] always is, a static linker may need to generate
PLT sequences that contain "bti c" as the first instruction. In effect:
bti c
adrp x16, page offset to .got.plt
...
Instead of:
adrp x16, page offset to .got.plt
...
At present the PLT decoding assumes the adrp will always be the first
instruction. This patch adds support for a single "bti c" to prefix it. A
test binary has been uploaded with such a PLT sequence. A forthcoming LLD
patch will make heavy use of the PLT decoding code.
Differential Revision: https://reviews.llvm.org/D62598
llvm-svn: 362523
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td')
0 files changed, 0 insertions, 0 deletions
