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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-05-25 17:34:58 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-05-25 17:34:58 +0000 |
| commit | 1cc499141266633240cb6090a29bc7d040e069bf (patch) | |
| tree | 9b89c8b74f7b306972b4f26a42e3dfb3233d50d0 /llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp | |
| parent | 7f08d12b0b02f02dcb48b459baa0cab5b5f62113 (diff) | |
| download | bcm5719-llvm-1cc499141266633240cb6090a29bc7d040e069bf.tar.gz bcm5719-llvm-1cc499141266633240cb6090a29bc7d040e069bf.zip | |
AMDGPU: Fix inconsistent lowering of select of vectors
f32 vectors would use a sequence of BFI instructions instead
of unrolled cmp + select. This was better in the case of a VALU
select with SGPR inputs, but we don't have a way of dealing with that
in the DAG.
llvm-svn: 270731
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp')
0 files changed, 0 insertions, 0 deletions
