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| author | Dan Gohman <dan433584@gmail.com> | 2015-11-25 19:36:19 +0000 |
|---|---|---|
| committer | Dan Gohman <dan433584@gmail.com> | 2015-11-25 19:36:19 +0000 |
| commit | fb3e0594e462272aeccdc69c55f243e4ee419dda (patch) | |
| tree | dc8f2c5d5c9e4a63ea41e051b6f80fc1eaad70d7 /llvm/lib/Target/WebAssembly/WebAssemblyInstrCall.td | |
| parent | 3275813d3590f9c45fbb55dd38719e2dc78da4ea (diff) | |
| download | bcm5719-llvm-fb3e0594e462272aeccdc69c55f243e4ee419dda.tar.gz bcm5719-llvm-fb3e0594e462272aeccdc69c55f243e4ee419dda.zip | |
[WebAssembly] Use a physical register to describe ARGUMENT liveness.
Instead of trying to move ARGUMENT instructions back up to the top after
they've been scheduled or sunk down, use a fake physical register to
create a liveness constraint that prevents ARGUMENT instructions from
moving down in the first place. This is still not entirely ideal, however
it is more robust than letting them move and moving them back.
llvm-svn: 254084
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyInstrCall.td')
| -rw-r--r-- | llvm/lib/Target/WebAssembly/WebAssemblyInstrCall.td | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrCall.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrCall.td index 530411b147d..4028460bd23 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrCall.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrCall.td @@ -12,6 +12,8 @@ /// //===----------------------------------------------------------------------===// +let Defs = [ARGUMENTS] in { + // The call sequence start/end LLVM-isms isn't useful to WebAssembly since it's // a virtual ISA. let isCodeGenOnly = 1 in { @@ -42,3 +44,5 @@ let Uses = [SP32, SP64], isCall = 1 in { [(WebAssemblycall0 I32:$callee)], "call_indirect\t$callee">; } // Uses = [SP32,SP64], isCall = 1 + +} // Defs = [ARGUMENTS] |

