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| author | Derek Schuff <dschuff@google.com> | 2018-08-07 21:24:01 +0000 |
|---|---|---|
| committer | Derek Schuff <dschuff@google.com> | 2018-08-07 21:24:01 +0000 |
| commit | 51ed131ed2e745a850f4283a96d25a48d6ee2f44 (patch) | |
| tree | ccbfeb4ac5566acf445a264b2d3584b38c4d81dd /llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp | |
| parent | dca675a0d8f4cbbaf2530b6b7e0bdda1b4a83600 (diff) | |
| download | bcm5719-llvm-51ed131ed2e745a850f4283a96d25a48d6ee2f44.tar.gz bcm5719-llvm-51ed131ed2e745a850f4283a96d25a48d6ee2f44.zip | |
[WebAssembly] Update SIMD binary arithmetic
Add missing SIMD types (v2f64) and binary ops. Also adds
tablegen support for automatically prepending prefix byte to SIMD
opcodes.
Differential Revision: https://reviews.llvm.org/D50292
Patch by Thomas Lively
llvm-svn: 339186
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp')
| -rw-r--r-- | llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp index 566ef68c027..20482c85446 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp @@ -134,7 +134,9 @@ private: case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: + case MVT::v2i64: case MVT::v4f32: + case MVT::v2f64: if (Subtarget->hasSIMD128()) return VT; break; @@ -678,10 +680,18 @@ bool WebAssemblyFastISel::fastLowerArguments() { Opc = WebAssembly::ARGUMENT_v4i32; RC = &WebAssembly::V128RegClass; break; + case MVT::v2i64: + Opc = WebAssembly::ARGUMENT_v2i64; + RC = &WebAssembly::V128RegClass; + break; case MVT::v4f32: Opc = WebAssembly::ARGUMENT_v4f32; RC = &WebAssembly::V128RegClass; break; + case MVT::v2f64: + Opc = WebAssembly::ARGUMENT_v2f64; + RC = &WebAssembly::V128RegClass; + break; case MVT::ExceptRef: Opc = WebAssembly::ARGUMENT_EXCEPT_REF; RC = &WebAssembly::EXCEPT_REFRegClass; @@ -782,11 +792,21 @@ bool WebAssemblyFastISel::selectCall(const Instruction *I) { IsDirect ? WebAssembly::CALL_v4i32 : WebAssembly::PCALL_INDIRECT_v4i32; ResultReg = createResultReg(&WebAssembly::V128RegClass); break; + case MVT::v2i64: + Opc = + IsDirect ? WebAssembly::CALL_v2i64 : WebAssembly::PCALL_INDIRECT_v2i64; + ResultReg = createResultReg(&WebAssembly::V128RegClass); + break; case MVT::v4f32: Opc = IsDirect ? WebAssembly::CALL_v4f32 : WebAssembly::PCALL_INDIRECT_v4f32; ResultReg = createResultReg(&WebAssembly::V128RegClass); break; + case MVT::v2f64: + Opc = + IsDirect ? WebAssembly::CALL_v2f64 : WebAssembly::PCALL_INDIRECT_v2f64; + ResultReg = createResultReg(&WebAssembly::V128RegClass); + break; case MVT::ExceptRef: Opc = IsDirect ? WebAssembly::CALL_EXCEPT_REF : WebAssembly::PCALL_INDIRECT_EXCEPT_REF; @@ -1297,9 +1317,15 @@ bool WebAssemblyFastISel::selectRet(const Instruction *I) { case MVT::v4i32: Opc = WebAssembly::RETURN_v4i32; break; + case MVT::v2i64: + Opc = WebAssembly::RETURN_v2i64; + break; case MVT::v4f32: Opc = WebAssembly::RETURN_v4f32; break; + case MVT::v2f64: + Opc = WebAssembly::RETURN_v2f64; + break; case MVT::ExceptRef: Opc = WebAssembly::RETURN_EXCEPT_REF; break; |
