summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
diff options
context:
space:
mode:
authorJF Bastien <jfb@google.com>2015-07-31 17:53:38 +0000
committerJF Bastien <jfb@google.com>2015-07-31 17:53:38 +0000
commit600aee98057e8657140713cd2a0dd6e5ff0247b8 (patch)
tree6c5e655f0da8454a616515d36ee2e63c0e968c7e /llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
parentbf1e5c0ee9256f0c0fc3f6dfad32c9cef81268a5 (diff)
downloadbcm5719-llvm-600aee98057e8657140713cd2a0dd6e5ff0247b8.tar.gz
bcm5719-llvm-600aee98057e8657140713cd2a0dd6e5ff0247b8.zip
WebAssembly: print basic integer assembly.
Summary: This prints assembly for int32 integer operations defined in WebAssemblyInstrInteger.td only, with major caveats: - The operation names are currently incorrect. - Other integer and floating-point types will be added later. - The printer isn't factored out to handle recursive AST code yet, since it can't even handle control flow anyways. - The assembly format isn't full s-expressions yet either, this will be added later. - This currently disables PrologEpilogCodeInserter as well as MachineCopyPropagation becasue they don't like virtual registers, which WebAssembly likes quite a bit. This will be fixed by factoring out NVPTX's change (currently a fork of PrologEpilogCodeInserter). Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11671 llvm-svn: 243763
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp')
-rw-r--r--llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp44
1 files changed, 39 insertions, 5 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
index 7a6c7784c54..e0e9a3b14bc 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
@@ -38,9 +38,11 @@ using namespace llvm;
namespace {
class WebAssemblyAsmPrinter final : public AsmPrinter {
+ const WebAssemblyInstrInfo *TII;
+
public:
WebAssemblyAsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
- : AsmPrinter(TM, std::move(Streamer)) {}
+ : AsmPrinter(TM, std::move(Streamer)), TII(nullptr) {}
private:
const char *getPassName() const override {
@@ -55,8 +57,10 @@ private:
AsmPrinter::getAnalysisUsage(AU);
}
- bool runOnMachineFunction(MachineFunction &F) override {
- return AsmPrinter::runOnMachineFunction(F);
+ bool runOnMachineFunction(MachineFunction &MF) override {
+ TII = static_cast<const WebAssemblyInstrInfo *>(
+ MF.getSubtarget().getInstrInfo());
+ return AsmPrinter::runOnMachineFunction(MF);
}
//===------------------------------------------------------------------===//
@@ -74,13 +78,43 @@ void WebAssemblyAsmPrinter::EmitInstruction(const MachineInstr *MI) {
SmallString<128> Str;
raw_svector_ostream OS(Str);
+ unsigned NumDefs = MI->getDesc().getNumDefs();
+ assert(NumDefs <= 1 &&
+ "Instructions with multiple result values not implemented");
+
+ if (NumDefs != 0) {
+ const MachineOperand &MO = MI->getOperand(0);
+ unsigned Reg = MO.getReg();
+ OS << "(setlocal @" << TargetRegisterInfo::virtReg2Index(Reg) << ' ';
+ }
+
+ OS << '(';
+
+ bool PrintOperands = true;
switch (MI->getOpcode()) {
+ case WebAssembly::ARGUMENT:
+ OS << "argument " << MI->getOperand(1).getImm();
+ PrintOperands = false;
+ break;
default:
- DEBUG(MI->print(dbgs()));
- llvm_unreachable("Unhandled instruction");
+ OS << TII->getName(MI->getOpcode());
break;
}
+ if (PrintOperands)
+ for (const MachineOperand &MO : MI->uses()) {
+ if (MO.isReg() && MO.isImplicit())
+ continue;
+ unsigned Reg = MO.getReg();
+ OS << " @" << TargetRegisterInfo::virtReg2Index(Reg);
+ }
+ OS << ')';
+
+ if (NumDefs != 0)
+ OS << ')';
+
+ OS << '\n';
+
OutStreamer->EmitRawText(OS.str());
}
OpenPOWER on IntegriCloud