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authorDan Gohman <dan433584@gmail.com>2015-09-09 00:52:47 +0000
committerDan Gohman <dan433584@gmail.com>2015-09-09 00:52:47 +0000
commit4f52e00ecbd6623360bd1ff132552a623052b88d (patch)
tree1d82943f473d505a0d62a1a4dcf225604156fb08 /llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
parent309915626110fffc66a6ee598f9d24dbbb256ded (diff)
downloadbcm5719-llvm-4f52e00ecbd6623360bd1ff132552a623052b88d.tar.gz
bcm5719-llvm-4f52e00ecbd6623360bd1ff132552a623052b88d.zip
[WebAssembly] Implement WebAssemblyInstrInfo::copyPhysReg
llvm-svn: 247110
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp')
-rw-r--r--llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp48
1 files changed, 26 insertions, 22 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
index eb1343292d3..c2e71c1489b 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
@@ -269,28 +269,32 @@ void WebAssemblyAsmPrinter::EmitInstruction(const MachineInstr *MI) {
OS << "(setlocal @" << TargetRegisterInfo::virtReg2Index(Reg) << ' ';
}
- OS << '(' << OpcodeName(TII, MI);
- for (const MachineOperand &MO : MI->uses())
- switch (MO.getType()) {
- default:
- llvm_unreachable("unexpected machine operand type");
- case MachineOperand::MO_Register: {
- if (MO.isImplicit())
- continue;
- unsigned Reg = MO.getReg();
- OS << " @" << TargetRegisterInfo::virtReg2Index(Reg);
- } break;
- case MachineOperand::MO_Immediate: {
- OS << ' ' << MO.getImm();
- } break;
- case MachineOperand::MO_FPImmediate: {
- OS << ' ' << toString(MO.getFPImm()->getValueAPF());
- } break;
- case MachineOperand::MO_GlobalAddress: {
- OS << ' ' << toSymbol(MO.getGlobal()->getName());
- } break;
- }
- OS << ')';
+ if (MI->getOpcode() == WebAssembly::COPY) {
+ OS << '@' << TargetRegisterInfo::virtReg2Index(MI->getOperand(1).getReg());
+ } else {
+ OS << '(' << OpcodeName(TII, MI);
+ for (const MachineOperand &MO : MI->uses())
+ switch (MO.getType()) {
+ default:
+ llvm_unreachable("unexpected machine operand type");
+ case MachineOperand::MO_Register: {
+ if (MO.isImplicit())
+ continue;
+ unsigned Reg = MO.getReg();
+ OS << " @" << TargetRegisterInfo::virtReg2Index(Reg);
+ } break;
+ case MachineOperand::MO_Immediate: {
+ OS << ' ' << MO.getImm();
+ } break;
+ case MachineOperand::MO_FPImmediate: {
+ OS << ' ' << toString(MO.getFPImm()->getValueAPF());
+ } break;
+ case MachineOperand::MO_GlobalAddress: {
+ OS << ' ' << toSymbol(MO.getGlobal()->getName());
+ } break;
+ }
+ OS << ')';
+ }
if (NumDefs != 0)
OS << ')';
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