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author | Jim Grosbach <grosbach@apple.com> | 2010-09-02 18:44:51 +0000 |
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committer | Jim Grosbach <grosbach@apple.com> | 2010-09-02 18:44:51 +0000 |
commit | 60409951285c2579d8e725542c327d29870f67e0 (patch) | |
tree | 0241bec15fce13ba836f09603b481be69660f132 /llvm/lib/Target/TargetRegisterInfo.cpp | |
parent | c79f50170a9a3c1740e39998acbaf45d6addcfd9 (diff) | |
download | bcm5719-llvm-60409951285c2579d8e725542c327d29870f67e0.tar.gz bcm5719-llvm-60409951285c2579d8e725542c327d29870f67e0.zip |
remove trailing whitespace
llvm-svn: 112847
Diffstat (limited to 'llvm/lib/Target/TargetRegisterInfo.cpp')
-rw-r--r-- | llvm/lib/Target/TargetRegisterInfo.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/TargetRegisterInfo.cpp b/llvm/lib/Target/TargetRegisterInfo.cpp index 6addbab851e..55f222c7c1c 100644 --- a/llvm/lib/Target/TargetRegisterInfo.cpp +++ b/llvm/lib/Target/TargetRegisterInfo.cpp @@ -63,7 +63,7 @@ TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const { /// getAllocatableSetForRC - Toggle the bits that represent allocatable /// registers for the specific register class. static void getAllocatableSetForRC(const MachineFunction &MF, - const TargetRegisterClass *RC, BitVector &R){ + const TargetRegisterClass *RC, BitVector &R){ for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), E = RC->allocation_order_end(MF); I != E; ++I) R.set(*I); |