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authorCraig Topper <craig.topper@intel.com>2018-02-01 17:08:39 +0000
committerCraig Topper <craig.topper@intel.com>2018-02-01 17:08:39 +0000
commit7e910a9e8503c58a858abf775fcc2cefe9b85db4 (patch)
tree8af5552a31f77f9cfb86ad4d0aab73375e25d9b6 /llvm/lib/Target/TargetMachine.cpp
parent657e5d8d41e7aae1cabfcb6e3200a9d4981a456e (diff)
downloadbcm5719-llvm-7e910a9e8503c58a858abf775fcc2cefe9b85db4.tar.gz
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[X86] Turn X86ISD::AND nodes that have no flag users back into ISD::AND just before isel to enable test instruction matching
Summary: EmitTest sometimes creates X86ISD::AND specifically to hide the AND from DAG combine. But this prevents isel patterns that look for (cmp (and X, Y), 0) from being able to see it. So we end up with an AND and a TEST. The TEST gets removed by compare instruction optimization during the peephole pass. This patch attempts to fix this by converting X86ISD::AND with no flag users back into ISD::AND during the DAG preprocessing just before isel. In order to do this correctly I had to make the X86ISD::AND node created by EmitTest in this case really have a flag output. Which arguably it should have had anyway so that the number of operands would be consistent for the opcode in all cases. Then I had to modify the ReplaceAllUsesWith to understand that we might be looking at an instruction with 2 outputs. Though in this case there are no uses to replace since we just created the node, but that's what the code did before so I just made it keep working. Reviewers: spatel, RKSimon, niravd, deadalnix Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42764 llvm-svn: 323982
Diffstat (limited to 'llvm/lib/Target/TargetMachine.cpp')
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