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| author | Chris Lattner <sabre@nondot.org> | 2006-02-21 23:11:00 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-02-21 23:11:00 +0000 |
| commit | 7bb4696dc3c55c18c5c580daa1c1f6b69f1322c9 (patch) | |
| tree | 052069c279b57ea506b4c8a4292bc9733011a2e2 /llvm/lib/Target/TargetLowering.cpp | |
| parent | ebb74895374ab13d2827118dcf0a7ca3189cc6c2 (diff) | |
| download | bcm5719-llvm-7bb4696dc3c55c18c5c580daa1c1f6b69f1322c9.tar.gz bcm5719-llvm-7bb4696dc3c55c18c5c580daa1c1f6b69f1322c9.zip | |
Updates to match change of getRegForInlineAsmConstraint prototype
llvm-svn: 26305
Diffstat (limited to 'llvm/lib/Target/TargetLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/TargetLowering.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/TargetLowering.cpp b/llvm/lib/Target/TargetLowering.cpp index 533499cbc0a..79211debc99 100644 --- a/llvm/lib/Target/TargetLowering.cpp +++ b/llvm/lib/Target/TargetLowering.cpp @@ -745,7 +745,8 @@ bool TargetLowering::isOperandValidForConstraint(SDOperand Op, std::vector<unsigned> TargetLowering:: -getRegForInlineAsmConstraint(const std::string &Constraint) const { +getRegForInlineAsmConstraint(const std::string &Constraint, + MVT::ValueType VT) const { // Not a physreg, must not be a register reference or something. if (Constraint[0] != '{') return std::vector<unsigned>(); assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); |
