summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/TargetLowering.cpp
diff options
context:
space:
mode:
authorChris Lattner <sabre@nondot.org>2006-05-05 22:32:12 +0000
committerChris Lattner <sabre@nondot.org>2006-05-05 22:32:12 +0000
commit0f64932a5c2c65fb9d6aa2ce488c282bb7a73cb5 (patch)
tree56d814b99428a6bb4db7d98825d2c831386d4366 /llvm/lib/Target/TargetLowering.cpp
parent8b9e11c1106d97874ea40d21ad99864fd2edd1e4 (diff)
downloadbcm5719-llvm-0f64932a5c2c65fb9d6aa2ce488c282bb7a73cb5.tar.gz
bcm5719-llvm-0f64932a5c2c65fb9d6aa2ce488c282bb7a73cb5.zip
Implement ComputeMaskedBits/SimplifyDemandedBits for ISD::TRUNCATE
llvm-svn: 28135
Diffstat (limited to 'llvm/lib/Target/TargetLowering.cpp')
-rw-r--r--llvm/lib/Target/TargetLowering.cpp18
1 files changed, 18 insertions, 0 deletions
diff --git a/llvm/lib/Target/TargetLowering.cpp b/llvm/lib/Target/TargetLowering.cpp
index 041d91ee72a..30ef67256f4 100644
--- a/llvm/lib/Target/TargetLowering.cpp
+++ b/llvm/lib/Target/TargetLowering.cpp
@@ -607,6 +607,16 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
break;
}
+ case ISD::TRUNCATE: {
+ if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask,
+ KnownZero, KnownOne, TLO, Depth+1))
+ return true;
+ assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
+ uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType());
+ KnownZero &= OutMask;
+ KnownOne &= OutMask;
+ break;
+ }
case ISD::AssertZext: {
MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
uint64_t InMask = MVT::getIntVTBitMask(VT);
@@ -864,6 +874,14 @@ void TargetLowering::ComputeMaskedBits(SDOperand Op, uint64_t Mask,
KnownZero, KnownOne, Depth+1);
return;
}
+ case ISD::TRUNCATE: {
+ ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
+ assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
+ uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType());
+ KnownZero &= OutMask;
+ KnownOne &= OutMask;
+ break;
+ }
case ISD::AssertZext: {
MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
uint64_t InMask = MVT::getIntVTBitMask(VT);
OpenPOWER on IntegriCloud